公开(公告)号：US10359825B2

公开(公告)日：2019-07-23

申请号：US15351644

申请日：2016-11-15

Applicant: Imagination Technologies Limited

Inventor： Iain Singleton ,  John Alexander Osborne Netterville ,  Ashish Darbari

IPC: G06F17/50 ,  G06F1/28 ,  G06F1/3234 ,  G06F1/12

Abstract: Methods, systems and hardware monitors for verifying that an integrated circuit defined by a hardware design meets a power requirement including detecting whether a power consuming transition has occurred for one or more flip-flops of an instantiation of the hardware design; in response to detecting that a power consuming transition has occurred, updating a count of power consuming transitions for the instantiation of the hardware design; and determining, whether the power requirement is met at a particular point in time by evaluating one or more properties that are based on the count of power consuming transitions.

公开(公告)号：US20180107537A1

公开(公告)日：2018-04-19

申请号：US15784746

申请日：2017-10-16

Applicant: Imagination Technologies Limited

Inventor： Ashish Darbari ,  Iain Singleton

IPC: G06F11/07

Abstract: Out-of-bounds recovery circuits configured to detect an out-of-bounds violation in an electronic device, and cause the electronic device to transition to a predetermined safe state when an out-of-bounds violation is detected. The out-of-bounds recovery circuits include detection logic configured to detect that an out-of-bounds violation has occurred when a processing element of the electronic device has fetched an instruction from an unallowable memory address range for the current operating state of the electronic device; and transition logic configured to cause the electronic device to transition to a predetermined safe state when an out-of-bounds violation has been detected by the detection logic.

公开(公告)号：US20170364609A1

公开(公告)日：2017-12-21

申请号：US15340638

申请日：2016-11-01

Applicant: Imagination Technologies Limited

Inventor： Ashish Darbari ,  Iain Singleton

IPC: G06F17/50 ,  G06F9/38 ,  G06F9/30

CPC classification number: G06F17/504 ,  G06F9/30145 ,  G06F9/3802 ,  G06F11/076 ,  G06F11/3055 ,  G06F17/5022 ,  G06F2217/14

Abstract: A hardware monitor arranged to detect livelock in a hardware design for an integrated circuit. The hardware monitor includes monitor and detection logic configured to detect when a particular state has occurred in an instantiation of the hardware design; and assertion evaluation logic configured to periodically evaluate one or more assertions that assert a formal property related to reoccurrence of the particular state in the instantiation of the hardware design to detect whether the instantiation of the hardware design is in a livelock comprising the predetermined state. The hardware monitor may be used by a formal verification tool to exhaustively verify that the instantiation of the hardware design cannot enter a livelock comprising the predetermined state.