公开(公告)号：US06938147B1

公开(公告)日：2005-08-30

申请号：US09309732

申请日：1999-05-11

申请人： William N. Joy ,  Marc Tremblay ,  Gary Lauterbach ,  Joseph I. Chamdani

发明人： William N. Joy ,  Marc Tremblay ,  Gary Lauterbach ,  Joseph I. Chamdani

IPC分类号： G06F9/38 ,  G06F9/48 ,  G06F9/00

CPC分类号： G06F9/4843 ,  G06F9/3851

摘要： A processor reduces wasted cycle time resulting from stalling and idling, and increases the proportion of execution time, by supporting and implementing both vertical multithreading and horizontal multithreading. Vertical multithreading permits overlapping or “hiding” of cache miss wait times. In vertical multithreading, multiple hardware threads share the same processor pipeline. A hardware thread is typically a process, a lightweight process, a native thread, or the like in an operating system that supports multithreading. Horizontal multithreading increases parallelism within the processor circuit structure, for example within a single integrated circuit die that makes up a single-chip processor. To further increase system parallelism in some processor embodiments, multiple processor cores are formed in a single die. Advances in on-chip multiprocessor horizontal threading are gained as processor core sizes are reduced through technological advancements.

摘要翻译： 处理器通过支持和实现垂直多线程和水平多线程来减少由于停滞和空闲而导致的浪费周期时间，并增加执行时间的比例。 垂直多线程允许重叠或“隐藏”高速缓存未命中等待时间。 在垂直多线程中，多个硬件线程共享相同的处理器管道。 在支持多线程的操作系统中，硬件线程通常是进程，轻量级进程，本机线程等。 水平多线程增加了处理器电路结构内的并行性，例如在构成单片处理器的单个集成电路管芯内。 为了在一些处理器实施例中进一步增加系统并行性，在单个管芯中形成多个处理器核。 通过技术进步降低了处理器核心尺寸，从而获得片上多处理器水平线程的进步。

公开(公告)号：US06420903B1

公开(公告)日：2002-07-16

申请号：US09638338

申请日：2000-08-14

申请人： Gajendra P. Singh ,  Joseph I. Chamdani ,  Renu Raman

发明人： Gajendra P. Singh ,  Joseph I. Chamdani ,  Renu Raman

IPC分类号： H03K1900

CPC分类号： G06F9/3851 ,  G06F9/3869

摘要： A vertical multi-threading processor includes one or more execution pipelines that are formed from a plurality of multiple-bit pipeline register flip-flops. The multiple-bit pipeline register flip-flops supply multiple storage bits. The individual bits of a multiple-bit pipeline register flip-flop store data for one of respective multiple threads or processes. When an executing (first) process stalls due to a stall condition, for example a cache miss, an active bit of the multiple-bit register flip-flop is stalled, removed from activity on the pipeline, and a previously inactive bit becomes active for executing a previously inactive (second) process. All states of the stalled first process are preserved in a temporarily inactive bit of the individual multiple-bit register flip-flop in each pipeline stage.

摘要翻译： 垂直多线程处理器包括由多个多位流水线寄存器触发器形成的一个或多个执行流水线。 多位流水线寄存器触发器提供多个存储位。 多位流水线寄存器触发器的各个比特存储相应多个线程或进程之一的数据。 当执行（第一）过程由于失速条件（例如高速缓存未命中）而停止时，多位寄存器触发器的活动位被停止，从流水线上的活动中移除，并且先前不活动的位变为活动 执行以前无效（第二）过程。 在每个流水线阶段，停止的第一进程的所有状态都保存在单个多位寄存器触发器的暂时不活动位中。

公开(公告)号：US6058466A

公开(公告)日：2000-05-02

申请号：US881732

申请日：1997-06-24

申请人： Ramesh Panwar ,  Joseph I. Chamdani

发明人： Ramesh Panwar ,  Joseph I. Chamdani

IPC分类号： G06F9/38 ,  G06F9/00

CPC分类号： G06F9/3806 ,  G06F9/3802 ,  G06F9/3844 ,  G06F9/3851 ,  G06F9/3863

摘要： A system of executing coded instructions in a dynamically configurable multiprocessor having shared execution resources including steps of placing a first processor in an active state upon booting of the multiprocessor. In response to a processor create command, a second processor is placed in an active state. When either the first or second processor encounter a cache miss that has to be serviced by off-chip cache the processor requiring service is placed in nap state in which instruction fetching for that processor is disabled. When either the first or second processor encounter a cache miss that has to be serviced by main memory, the processor requiring services is placed in a sleep state by flushing all instructions from the processor in the sleep state and disabling instruction fetching for the processor in the sleep state.

摘要翻译： 在具有共享执行资源的动态可配置多处理器中执行编码指令的系统，包括在引导多处理器时将第一处理器置于活动状态的步骤。 响应于处理器创建命令，第二处理器被置于活动状态。 当第一或第二处理器遇到必须由片外高速缓存服务的高速缓存未命中时，处理器需要服务处于休眠状态，在该状态下禁止该处理器的指令取出。 当第一或第二处理器遇到必须由主存储器服务的高速缓存未命中时，需要服务的处理器通过在睡眠状态下从处理器中冲洗所有指令而置于休眠状态，并且禁用在处理器中的指令获取 睡眠状态

公开(公告)号：US6035374A

公开(公告)日：2000-03-07

申请号：US881239

申请日：1997-06-25

申请人： Ramesh Panwar ,  Joseph I. Chamdani

发明人： Ramesh Panwar ,  Joseph I. Chamdani

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3885 ,  G06F9/3806 ,  G06F9/382 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3851 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3861

摘要： A method of executing coded instructions in a dynamically configurable multiprocessor having shared execution resources including steps of placing a first processor in an active state upon booting of the multiprocessor. In response to a processor create command, a second processor is placed in an active state. When either the first or second processor encounter a cache miss that has to be serviced by off-chip cache the processor requiring service is placed in nap state in which instruction fetching for that processor is disabled. When either the first or second processor encounter a cache miss that has to be serviced by main memory, the processor requiring services I placed in a sleep state by flushing all instructions from the processor in the sleep state and disabling instruction fetching for the processor in the sleep state.

摘要翻译： 一种在具有共享执行资源的动态可配置多处理器中执行编码指令的方法，包括在所述多处理器引导时将第一处理器置于活动状态的步骤。 响应于处理器创建命令，第二处理器被置于活动状态。 当第一或第二处理器遇到必须由片外高速缓存服务的高速缓存未命中时，处理器需要服务处于休眠状态，在该状态下禁止该处理器的指令取出。 当第一或第二处理器遇到必须由主存储器服务的高速缓存未命中时，处理器要求服务I处于睡眠状态，通过在处于休眠状态的状态下冲洗所有指令并禁止在处理器中取出指令 睡眠状态