公开(公告)号：US08898436B2

公开(公告)日：2014-11-25

申请号：US12426550

申请日：2009-04-20

Applicant: Shailender Chaudhry ,  Marc Tremblay

Inventor： Shailender Chaudhry ,  Marc Tremblay

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30098 ,  G06F9/30112 ,  G06F9/30138 ,  G06F9/3838 ,  G06F9/384

Abstract: A register file, in a processor, includes a first plurality of registers of a first size, n-bits. A decoder uses a mapping that divides the register file into a second plurality M of registers having a second size. Each of the registers having the second size is assigned a different name in a continuous name space. Each register of the second size includes a plurality N of registers of the first size, n-bits. Each register in the plurality N of registers is assigned the same name as the register of the second size that includes that plurality. State information is maintained in the register file for each n-bit register. The dependence of an instruction on other instructions is detected through the continuous name space. The state information allows the processor to determine when the information in any portion, or all, of a register is valid.

Abstract translation: 在处理器中的寄存器文件包括第一大小的n位的第一多个寄存器。 解码器使用将寄存器文件分成具有第二大小的第二多个寄存器M的映射。 具有第二大小的每个寄存器在连续的名称空间中被分配不同的名称。 第二大小的每个寄存器包括多个N个第一大小的寄存器，n位。 多个N个寄存器中的每个寄存器被分配与包括该多个寄存器的第二大小的寄存器相同的名称。 状态信息保存在每个n位寄存器的寄存器文件中。 通过连续名称空间检测指令对其他指令的依赖性。 状态信息允许处理器确定寄存器的任何部分或全部中的信息何时有效。

公开(公告)号：US20120331314A1

公开(公告)日：2012-12-27

申请号：US13529761

申请日：2012-06-21

Applicant: Shailender Chaudhry ,  Quinn A. Jacobson ,  Marc Tremblay

Inventor： Shailender Chaudhry ,  Quinn A. Jacobson ,  Marc Tremblay

IPC: G06F1/32

CPC classification number: G06F9/3867 ,  G06F1/206 ,  G06F1/3203 ,  G06F9/3869 ,  Y02D10/16

Abstract: A processor includes a device providing a throttling power output signal. The throttling power output signal is used to determine when to logically throttle the power consumed by the processor. At least one core in the processor includes a pipeline having a decode pipe; and a logical power throttling unit coupled to the device to receive the output signal, and coupled to the decode pipe. Following the logical power throttling unit receiving the power throttling output signal satisfying a predetermined criterion, the logical power throttling unit causes the decode pipe to reduce an average number of instructions decoded per processor cycle without physically changing the processor cycle or any processor supply voltages.

Abstract translation: 处理器包括提供节流功率输出信号的装置。 节流电源输出信号用于确定何时逻辑地调节处理器消耗的功率。 处理器中的至少一个核心包括具有解码管道的管线; 以及耦合到所述设备以接收所述输出信号并且耦合到所述解码管的逻辑功率节流单元。 在接收到满足预定标准的功率节流输出信号的逻辑功率节流单元之后，逻辑功率节流单元使得解码管减少在每个处理器周期解码的平均指令数，而不物理地改变处理器周期或任何处理器供电电压。

公开(公告)号：US07818510B2

公开(公告)日：2010-10-19

申请号：US11832777

申请日：2007-08-02

Applicant: Marc Tremblay ,  Quinn A. Jacobson ,  Shailender Chaudhry

Inventor： Marc Tremblay ,  Quinn A. Jacobson ,  Shailender Chaudhry

IPC: G06F12/14

CPC classification number: G06F12/0862 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3857 ,  G06F9/467 ,  G06F12/0815

Abstract: One embodiment of the present invention provides a system that selectively monitors store instructions to support transactional execution of a process, wherein changes made during the transactional execution are not committed to the architectural state of a processor until the transactional execution successfully completes. Upon encountering a store instruction during transactional execution of a block of instructions, the system determines whether the store instruction is a monitored store instruction or an unmonitored store instruction. If the store instruction is a monitored store instruction, the system performs the store operation, and store-marks a cache line associated with the store instruction to facilitate subsequent detection of an interfering data access to the cache line from another process. If the store instruction is an unmonitored store instruction, the system performs the store operation without store-marking the cache line.

Abstract translation: 本发明的一个实施例提供了一种系统，其选择性地监视存储指令以支持进程的事务性执行，其中在事务执行期间进行的改变不被提交到处理器的体系结构状态，直到事务执行成功完成。 在交易执行指令块期间遇到存储指令时，系统确定存储指令是监视存储指令还是非监视存储指令。 如果存储指令是监视的存储指令，则系统执行存储操作，并存储与存储指令相关联的高速缓存行，以便随后检测到来自另一进程的高速缓存行的干扰数据访问。 如果存储指令是不受监视的存储指令，则系统执行存储操作而不存储标记高速缓存行。

公开(公告)号：US20100250918A1

公开(公告)日：2010-09-30

申请号：US12726849

申请日：2010-03-18

Applicant: Marc TREMBLAY ,  Sousso KELOUWANI ,  Eric MELIN

Inventor： Marc TREMBLAY ,  Sousso KELOUWANI ,  Eric MELIN

IPC: G06N5/02 ,  H04L9/00 ,  G06F15/18

CPC classification number: H04L63/0428 ,  H04L47/2441 ,  H04L63/0245 ,  H04L63/1425 ,  H04L63/166

Abstract: The present relates to a method and a system for identifying an application type from encrypted traffic transported over an IP network. The method and system extract at least a portion of IP flow parameters from the encrypted traffic using at least one of specific target encryption types. Then, the method and system transmit the extracted IP flow parameters to a learning-based classification engine. The learning-based classification engine has been trained with unencrypted traffic. Then, the method and system infer at least one corresponding application type for the extracted IP flow parameters.

Abstract translation: 本发明涉及一种用于通过IP网络传送的加密业务识别应用类型的方法和系统。 所述方法和系统使用特定目标加密类型中的至少一种从加密流量提取至少一部分IP流参数。 然后，该方法和系统将所提取的IP流参数发送到基于学习的分类引擎。 基于学习的分类引擎已经通过未加密的流量训练。 然后，该方法和系统推断出所提取的IP流参数的至少一个对应的应用类型。

公开(公告)号：US07711928B2

公开(公告)日：2010-05-04

申请号：US11082282

申请日：2005-03-16

Applicant: Marc Tremblay ,  Shailender Chaudhry ,  Quinn A. Jacobson

Inventor： Marc Tremblay ,  Shailender Chaudhry ,  Quinn A. Jacobson

IPC: G06F9/30

CPC classification number: G06F9/30061 ,  G06F9/383 ,  G06F9/3838 ,  G06F9/3842

Abstract: A user is provided with means to sample memory hierarchy via software. This allows a user to enhance memory-level parallelism via software. A status of information needed for execution of a second computer program instruction is read in response to execution of a first computer program instruction. Execution continues with execution of the second computer program instruction upon the status being a first status. Alternatively, a third computer program instruction is executed upon the status being a second status different from the first status. Thus, execution of the first computer program instruction allows control of the memory hierarchy, which in turn give the user control of the memory hierarchy.

Abstract translation: 为用户提供了通过软件对存储器层次结构进行抽样的方法。 这允许用户通过软件来增强内存级并行性。 响应于第一计算机程序指令的执行，读取执行第二计算机程序指令所需的信息的状态。 在状态为第一状态时，继续执行第二计算机程序指令。 或者，在状态是与第一状态不同的第二状态的情况下执行第三计算机程序指令。 因此，第一计算机程序指令的执行允许对存储器层次的控制，这进而使得用户对存储器层级进行控制。

公开(公告)号：US20090254905A1

公开(公告)日：2009-10-08

申请号：US12061554

申请日：2008-04-02

Applicant: Sherman H. Yip ,  Paul Caprioli ,  Marc Tremblay

Inventor： Sherman H. Yip ,  Paul Caprioli ,  Marc Tremblay

IPC: G06F9/46

CPC classification number: G06F9/466 ,  G06F9/3842 ,  G06F9/3851 ,  G06F12/0842

Abstract: Embodiments of the present invention provide a system that executes a transaction on a simultaneous speculative threading (SST) processor. In these embodiments, the processor includes a primary strand and a subordinate strand. Upon encountering a transaction with the primary strand while executing instructions non-transactionally, the processor checkpoints the primary strand and executes the transaction with the primary strand while continuing to non-transactionally execute deferred instructions with the subordinate strand. When the subordinate strand non-transactionally accesses a cache line during the transaction, the processor updates a record for the cache line to indicate the first strand ID. When the primary strand transactionally accesses a cache line during the transaction, the processor updates a record for the cache line to indicate a second strand ID.

Abstract translation: 本发明的实施例提供了一种在同时推测的线程（SST）处理器上执行交易的系统。 在这些实施例中，处理器包括主链和从属链。 在非事务性地执行指令的同时遇到与主链的事务时，处理器检查主链，并与主链一起执行事务，同时继续非事务地执行与下级链的延迟指令。 当下级链在事务期间非事务地访问高速缓存行时，处理器更新用于高速缓存行的记录以指示第一个链ID。 当主链在事务期间事务地访问高速缓存行时，处理器更新用于高速缓存行的记录以指示第二个链ID。

公开(公告)号：US07587581B2

公开(公告)日：2009-09-08

申请号：US11710112

申请日：2007-02-23

Applicant: William N. Joy ,  Marc Tremblay ,  Gary Lauterbach ,  Joseph I. Chamdani

Inventor： William N. Joy ,  Marc Tremblay ,  Gary Lauterbach ,  Joseph I. Chamdani

IPC: G06F9/38

CPC classification number: G06F9/30141 ,  G06F9/30127 ,  G06F9/3804 ,  G06F9/3851 ,  G06F9/3885 ,  G06F9/4843 ,  G06F12/0842

Abstract: A processor reduces wasted cycle time resulting from stalling and idling, and increases the proportion of execution time, by supporting and implementing both vertical multithreading and horizontal multithreading. Vertical multithreading permits overlapping or “hiding” of cache miss wait times. In vertical multithreading, multiple hardware threads share the same processor pipeline. A hardware thread is typically a process, a lightweight process, a native thread, or the like in an operating system that supports multithreading. Horizontal multithreading increases parallelism within the processor circuit structure, for example within a single integrated circuit die that makes up a single-chip processor. To further increase system parallelism in some processor embodiments, multiple processor cores are formed in a single die. Advances in on-chip multiprocessor horizontal threading are gained as processor core sizes are reduced through technological advancements.

Abstract translation: 处理器通过支持和实现垂直多线程和水平多线程来减少由于停滞和空闲而导致的浪费周期时间，并增加执行时间的比例。 垂直多线程允许重叠或“隐藏”高速缓存未命中等待时间。 在垂直多线程中，多个硬件线程共享相同的处理器管道。 在支持多线程的操作系统中，硬件线程通常是进程，轻量级进程，本机线程等。 水平多线程增加了处理器电路结构内的并行性，例如在构成单片处理器的单个集成电路管芯内。 为了在一些处理器实施例中进一步增加系统并行性，在单个管芯中形成多个处理器核。 通过技术进步降低了处理器核心尺寸，从而获得片上多处理器水平线程的进步。

公开(公告)号：US07490228B2

公开(公告)日：2009-02-10

申请号：US11369212

申请日：2006-03-06

Applicant: Marc Tremblay ,  William Joy

Inventor： Marc Tremblay ,  William Joy

IPC: G06F9/40

CPC classification number: G06F9/30043 ,  G06F9/30105 ,  G06F9/3012 ,  G06F9/3851 ,  G06F9/462 ,  G06F9/463

Abstract: A processor including a large register file utilizes a dirty bit storage coupled to the register file and a dirty bit logic that controls resetting of the dirty bit storage. The dirty bit logic determines whether a register or group of registers in the register file has been written since the process was loaded or the context was last restored and, if written generates a value in the dirty bit storage that designates the written condition of the register or group of registers. When the context is next saved, the dirty bit logic saves a particular register or group of registers when the dirty bit storage indicates that a register or group of registers was written. If the register or group of registers was not written, the context is switched without saving the register or group of registers. The dirty bit storage is initialized when a process is loaded or the context changes.

Abstract translation: 包括大寄存器文件的处理器利用耦合到寄存器文件的脏位存储器和控制脏位存储器的复位的脏位逻辑。 脏位逻辑确定寄存器文件中的寄存器或寄存器组是否已被写入，因为进程被加载或上下文被上次恢复，并且如果写入，则在指定寄存器的写入条件的脏位存储器中生成一个值 或一组寄存器。 当下一个保存上下文时，脏位逻辑在脏位存储器指示写入寄存器或寄存器组时，保存特定寄存器或寄存器组。 如果寄存器或寄存器组未写入，则上下文切换而不保存寄存器或寄存器组。 当加载进程或上下文更改时，脏位存储将被初始化。

公开(公告)号：US07484080B2

公开(公告)日：2009-01-27

申请号：US11103912

申请日：2005-04-11

Applicant: Shailender Chaudhry ,  Marc Tremblay ,  Paul Caprioli

Inventor： Shailender Chaudhry ,  Marc Tremblay ,  Paul Caprioli

IPC: G06F9/00

CPC classification number: G06F9/3863 ,  G06F9/383 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3857 ,  G06F9/3865

Abstract: One embodiment of the present invention provides a system that facilitates deferring execution of instructions with unresolved data dependencies as they are issued for execution in program order. During a normal execution mode, the system issues instructions for execution in program order. Upon encountering an unresolved data dependency during execution of an instruction, the system generates a checkpoint that can subsequently be used to return execution of the program to the point of the instruction. Next, the system executes the instruction and subsequent instructions in an execute-ahead mode, wherein instructions that cannot be executed because of an unresolved data dependency are deferred, and wherein other non-deferred instructions are executed in program order. Upon encountering a store during the execute-ahead mode, the system determines if the store buffer is full. If so, the system prefetches a cache line for the store, and defers execution of the store. If the number of stores that are encountered during execute-ahead mode exceeds the capacity of the store buffer, which means that the store buffer will never have additional space to accept additional stores during the execute-ahead mode because the store buffer is gated, the system directly enters the scout mode, without waiting for the deferred queue to eventually fill.

Abstract translation: 本发明的一个实施例提供了一种系统，其有助于在按照程序顺序执行时，推迟执行具有未解决的数据依赖性的指令。 在正常执行模式下，系统以程序顺序发出执行指令。 在执行指令期间遇到未解决的数据依赖性时，系统产生一个检查点，随后可以使用该检查点将程序的执行返回到指令点。 接下来，系统以执行模式执行指令和后续指令，其中由于未解决的数据依赖性而不能执行的指令被延迟，并且其中以程序顺序执行其他非延迟指令。 在执行提前模式期间遇到存储器时，系统确定存储缓冲区是否已满。 如果是这样，系统将预取商店的高速缓存线，并延迟商店的执行。 如果在执行超前模式期间遇到的存储的数量超过了存储缓冲区的容量，这意味着由于存储缓冲区被选通，在执行提前模式下，存储缓冲区将永远不会有额外的空间来接受附加存储， 系统直接进入侦察模式，无需等待延期队列最终填满。

公开(公告)号：US07469334B1

公开(公告)日：2008-12-23

申请号：US11095643

申请日：2005-03-30

Applicant: Shailender Chaudhry ,  Marc Tremblay ,  Quinn A. Jacobson

Inventor： Shailender Chaudhry ,  Marc Tremblay ,  Quinn A. Jacobson

IPC: G06F9/44

CPC classification number: G06F9/3863 ,  G06F9/3867

Abstract: One embodiment of the present invention provides a system that facilitates a fast execution restart following speculative execution. During normal operation of the system, a processor executes code on a non-speculative mode. Upon encountering a stall condition, the system checkpoints the state of the processor and executes the code in a speculative mode from the point of the stall. As the processor commences execution in speculative mode, it stores copies of instructions as they are issued into a recovery queue. When the stall condition is ultimately resolved, execution in non-speculative mode is recommenced and the execution units are initially loaded with instructions from the recovery queue, thereby avoiding the delay involved in waiting for instructions to propagate through the fetch and the decode stages of the pipeline. At the same time, the processor begins fetching subsequent instructions following the last instruction in the recovery queue. When all the instructions have been loaded from the recovery queue, the execution units begin receiving the subsequent instructions that have propagated through the fetch and decode stages of the pipeline.

Abstract translation: 本发明的一个实施例提供一种促进在推测执行之后的快速执行重新启动的系统。 在系统的正常操作期间，处理器以非推测模式执行代码。 在遇到停顿状态时，系统检查处理器的状态，并从失速点以推测模式执行代码。 当处理器以推测模式开始执行时，它会将指令的副本存储在恢复队列中。 当失速状态最终得到解决时，重新开始非推测模式的执行，并且执行单元最初被加载有来自恢复队列的指令，从而避免等待指令通过读取和解码阶段传播的延迟 管道。 同时，处理器开始在恢复队列中的最后一条指令之后提取后续指令。 当从恢复队列中加载所有指令时，执行单元开始接收通过流水线的读取和解码阶段传播的后续指令。