公开(公告)号：US07480835B2

公开(公告)日：2009-01-20

申请号：US11440315

申请日：2006-05-24

申请人： Kang Wu ,  Wei Zhang ,  Jun Huang

发明人： Kang Wu ,  Wei Zhang ,  Jun Huang

IPC分类号： G06F11/00

CPC分类号： G06F11/24

摘要： A system and method for testing a link control card (LCC) includes a host, a middle plane (MP), and an array having a plurality of testing devices. The host is connected to the LCC for transmitting signals, and the host is connected to the array for sending out commands and receiving results. The MP is connected between the LCC and the testing device array. Each of the testing devices includes a micro-controller unit (MCU), a connector connected to the MCU for receiving the signals, a hub connected to the connector for testing the signals, a voltage margin control unit connected to the MCU for controlling a voltage margin of the LCC, an address setting unit connected to the MCU, and a first interface connected to the MCU for outputting results.

摘要翻译： 用于测试链路控制卡（LCC）的系统和方法包括主机，中间平面（MP）和具有多个测试设备的阵列。 主机连接到LCC发送信号，主机连接到阵列发送命令和接收结果。 MP连接在LCC和测试设备阵列之间。 每个测试装置包括微控制器单元（MCU），连接到MCU的用于接收信号的连接器，连接到连接器的用于测试信号的集线器，连接到MCU的电压余量控制单元，用于控制电压 LCC的余量，连接到MCU的地址设置单元，以及连接到MCU的第一接口，用于输出结果。

公开(公告)号：US20070109002A1

公开(公告)日：2007-05-17

申请号：US11440318

申请日：2006-05-24

申请人： Kang Wu ,  Wei Zhang ,  Jun Huang ,  Li Ding

发明人： Kang Wu ,  Wei Zhang ,  Jun Huang ,  Li Ding

IPC分类号： G01R31/02

CPC分类号： H04L43/50

摘要： A system and method for testing a Link Control Card (LCC) of a storage device includes a host, a middle plane (MP), a switch, and a testing device array. The host is connected to the testing device array for sending out command sets and receiving results. The MP is connected between the LCC and the testing device array. The switch determines the LCC to output hard reset signals and the hard reset signals are transferred to the testing device array via the MP. The testing device array includes a plurality of testing devices, and each of the testing devices includes a micro-controller unit (MCU); a connector being connected to the MCU, and coupled to the MP; an address setting unit being connected to the MCU, for setting an unique address of each of the testing devices; and a first interface being connected to the MCU for outputting results.

摘要翻译： 用于测试存储设备的链路控制卡（LCC）的系统和方法包括主机，中间平面（MP），交换机和测试设备阵列。 主机连接到测试设备阵列，用于发送命令集和接收结果。 MP连接在LCC和测试设备阵列之间。 该开关确定LCC输出硬复位信号，硬复位信号通过MP传输到测试器件阵列。 测试装置阵列包括多个测试装置，并且每个测试装置包括微控制器单元（MCU）; 连接器连接到MCU，并连接到MP; 连接到MCU的地址设置单元，用于设置每个测试设备的唯一地址; 以及连接到MCU的第一接口，用于输出结果。

公开(公告)号：US20070018668A1

公开(公告)日：2007-01-25

申请号：US11440315

申请日：2006-05-24

申请人： Kang Wu ,  Wei Zhang ,  Jun Huang

发明人： Kang Wu ,  Wei Zhang ,  Jun Huang

IPC分类号： G01R31/02

CPC分类号： G06F11/24

摘要： A system and method for testing a link control card (LCC) includes a host, a middle plane (MP), and an array having a plurality of testing devices. The host is connected to the LCC for transmitting signals, and the host is connected to the array for sending out commands and receiving results. The MP is connected between the LCC and the testing device array. Each of the testing devices includes a micro-controller unit (MCU), a connector connected to the MCU for receiving the signals, a hub connected to the connector for testing the signals, a voltage margin control unit connected to the MCU for controlling a voltage margin of the LCC, an address setting unit connected to the MCU, and a first interface connected to the MCU for outputting results.

摘要翻译： 用于测试链路控制卡（LCC）的系统和方法包括主机，中间平面（MP）和具有多个测试设备的阵列。 主机连接到LCC发送信号，主机连接到阵列发送命令和接收结果。 MP连接在LCC和测试设备阵列之间。 每个测试装置包括微控制器单元（MCU），连接到MCU的用于接收信号的连接器，连接到连接器的用于测试信号的集线器，连接到MCU的电压余量控制单元，用于控制电压 LCC的余量，连接到MCU的地址设置单元，以及连接到MCU的第一接口，用于输出结果。

公开(公告)号：US06941497B2

公开(公告)日：2005-09-06

申请号：US10047344

申请日：2002-01-15

申请人： Kang Wu ,  Susan L. Stirrat

发明人： Kang Wu ,  Susan L. Stirrat

IPC分类号： G01R31/3183 ,  G06F11/22 ,  H01L21/66 ,  G01R31/28

CPC分类号： G01R31/31835 ,  G06F11/2273

摘要： An N2 algorithm for optimizing correlated events, applicable to the optimization of the detection of redundant tests and inefficient tests (RIT's), is disclosed. This algorithm represents a set of N tests with L defects as N L-dimensional correlation vectors. The N2 algorithm optimizes in terms of the minimum set of vectors, and the set of vectors that take the minimum time to detect the L defects. The minimum set optimization determines a set of vectors (tests) that contains the minimum number of vectors (tests) by analyzing the correlation among the N vectors. This minimum set optimization provides the minimum test set containing all defects in an algorithm that takes O(N2) operations. The minimum time optimization determines a sequence of vectors (tests) that will detect the defects in a minimum amount of time. Taking into the account of the different execution time of each vector (test), the algorithm analyzes the complicated correlation among the vectors (tests) and gives an optimized sequence of vectors (tests) within O(N2) operations. The optimized sequence of vectors (tests) takes a minimum amount of time to find all the defects.

摘要翻译： 公开了一种用于优化相关事件的适用于优化冗余测试和低效测试（RIT's）的优化的N 2 2算法。 该算法表示具有L个缺陷的N个测试集作为N个L维相关向量。 N？2？算法根据最小矢量集和最小时间来检测L个缺陷的向量组进行优化。 最小集优化通过分析N个向量之间的相关性来确定包含最小数目向量（测试）的一组向量（测试）。 这种最小设置优化提供了包含所有缺陷的最小测试集，该算法采用O（N <2> 0）操作。 最小时间优化确定将在最短时间内检测缺陷的向量（测试）序列。 考虑到每个向量的不同执行时间（测试），该算法分析了向量（测试）之间的复杂相关性，并给出了O（N <2> 0）内的向量（测试）优化序列 ）操作。 优化的载体序列（测试）需要最少的时间来找到所有缺陷。