公开(公告)号：US07464354B2

公开(公告)日：2008-12-09

申请号：US11297308

申请日：2005-12-08

申请人： Parag Birmiwal ,  Sundeep Chadha ,  Tilman Gloekler ,  Johannes Koesters

发明人： Parag Birmiwal ,  Sundeep Chadha ,  Tilman Gloekler ,  Johannes Koesters

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G01R31/318357 ,  G01R31/318328

摘要： An apparatus for performing temporal checking is disclosed. A signal logger for performing temporal checking includes a group of edge detection modules and a group of counting modules. During testing, the signal logger is coupled to a device under testing (DUT). Each of the edge detection modules is capable of maintaining edge information after a state transition on a signal within the DUT has been detected. Each of the counting modules is associated with one of the edge detection modules. Each of the countering modules is capable of maintaining a clock cycle count information associated with a detected edge. After the testing has been completed, temporal checking information on a signal within the DUT can be obtained by reconstructing the edge information and the associated clock cycle count information of the signal collected during the test.

摘要翻译： 公开了一种用于进行时间检查的装置。 用于执行时间检查的信号记录器包括一组边缘检测模块和一组计数模块。 在测试期间，信号记录器耦合到被测设备（DUT）。 每个边缘检测模块能够在检测到DUT内的信号的状态转换之后保持边缘信息。 每个计数模块与边缘检测模块之一相关联。 每个对抗模块能够维持与检测到的边缘相关联的时钟周期计数信息。 在测试完成之后，可以通过重建在测试期间收集的信号的边缘信息和相关联的时钟周期计数信息来获得DUT内的信号的时间检查信息。

公开(公告)号：US20080195340A1

公开(公告)日：2008-08-14

申请号：US12102525

申请日：2008-04-14

申请人： Parag Birmiwal ,  Sundeep Chadha ,  Tilman Gloekler ,  Johannes Koesters

发明人： Parag Birmiwal ,  Sundeep Chadha ,  Tilman Gloekler ,  Johannes Koesters

IPC分类号： G01R31/00

CPC分类号： G01R31/318357 ,  G01R31/318328

摘要： An apparatus for performing temporal checking is disclosed. A signal logger for performing temporal checking includes a group of edge detection modules and a group of counting modules. During testing, the signal logger is coupled to a device under testing (DUT). Each of the edge detection modules is capable of maintaining edge information after a state transition on a signal within the DUT has been detected. Each of the counting modules is associated with one of the edge detection modules. Each of the countering modules is capable of maintaining a clock cycle count information associated with a detected edge. After the testing has been completed, temporal checking information on a signal within the DUT can be obtained by reconstructing the edge information and the associated clock cycle count information of the signal collected during the test.

摘要翻译： 公开了一种用于进行时间检查的装置。 用于执行时间检查的信号记录器包括一组边缘检测模块和一组计数模块。 在测试期间，信号记录器耦合到被测设备（DUT）。 每个边缘检测模块能够在检测到DUT内的信号的状态转换之后保持边缘信息。 每个计数模块与边缘检测模块之一相关联。 每个对抗模块能够维持与检测到的边缘相关联的时钟周期计数信息。 在测试完成之后，可以通过重建在测试期间收集的信号的边缘信息和相关联的时钟周期计数信息来获得DUT内的信号的时间检查信息。

公开(公告)号：US20080141071A1

公开(公告)日：2008-06-12

申请号：US11608911

申请日：2006-12-11

申请人： Stephen C. Bergman ,  Tilman Gloekler ,  Klaus Heinzelmann ,  Ulla Herter ,  Karl Heinz Uhl

发明人： Stephen C. Bergman ,  Tilman Gloekler ,  Klaus Heinzelmann ,  Ulla Herter ,  Karl Heinz Uhl

IPC分类号： G06F11/34

CPC分类号： G06F11/3476 ,  G06F17/5022

摘要： A computer implemented method, system and computer program product for providing a waveform trace of a last plurality of cycles of a simulation prior to occurrence of an error in the simulation. A computer implemented method in a data processing system for providing a waveform trace for a last plurality of cycles of a simulation prior to occurrence of an error in the simulation includes storing history information relating to a last plurality of cycles of a simulation during running of the simulation. Responsive to an error occurring in the simulation, the simulation is stopped, and a waveform trace for the last plurality of cycles of the simulation is provided using the stored history information.

摘要翻译： 一种计算机实现的方法，系统和计算机程序产品，用于在模拟中发生错误之前提供模拟的最后多个循环的波形轨迹。 数据处理系统中的计算机实现的方法，用于在仿真发生之前的模拟的最后多个循环中提供波形轨迹，包括存储关于模拟运行期间最后多个周期的历史信息 模拟。 响应于仿真中发生的错误，停止仿真，并且使用存储的历史信息提供用于模拟的最后多个周期的波形跟踪。