Pre-Mortem Waveform Trace Generation for Hardware Description Language Simulators
    1.
    发明申请
    Pre-Mortem Waveform Trace Generation for Hardware Description Language Simulators 审中-公开
    硬件描述语言模拟器的先验波形跟踪生成

    公开(公告)号:US20080141071A1

    公开(公告)日:2008-06-12

    申请号:US11608911

    申请日:2006-12-11

    IPC分类号: G06F11/34

    CPC分类号: G06F11/3476 G06F17/5022

    摘要: A computer implemented method, system and computer program product for providing a waveform trace of a last plurality of cycles of a simulation prior to occurrence of an error in the simulation. A computer implemented method in a data processing system for providing a waveform trace for a last plurality of cycles of a simulation prior to occurrence of an error in the simulation includes storing history information relating to a last plurality of cycles of a simulation during running of the simulation. Responsive to an error occurring in the simulation, the simulation is stopped, and a waveform trace for the last plurality of cycles of the simulation is provided using the stored history information.

    摘要翻译: 一种计算机实现的方法,系统和计算机程序产品,用于在模拟中发生错误之前提供模拟的最后多个循环的波形轨迹。 数据处理系统中的计算机实现的方法,用于在仿真发生之前的模拟的最后多个循环中提供波形轨迹,包括存储关于模拟运行期间最后多个周期的历史信息 模拟。 响应于仿真中发生的错误,停止仿真,并且使用存储的历史信息提供用于模拟的最后多个周期的波形跟踪。

    Scan verification for a scan-chain device under test
    2.
    发明授权
    Scan verification for a scan-chain device under test 有权
    对正在测试的扫描链设备进行扫描验证

    公开(公告)号:US07386775B2

    公开(公告)日:2008-06-10

    申请号:US11206846

    申请日:2005-08-18

    IPC分类号: G01R31/28 G06F11/00

    CPC分类号: G01R31/318583

    摘要: Methods, apparatus, and products are disclosed for scan verification for a simulated device under test (‘DUT’), the DUT having scan chains, scan inputs, and scan outputs that include verifying correct data entry from the scan inputs of the DUT into the beginning of the scan chain, verifying correct propagation of scan data in the scan chain between the scan inputs and the scan outputs, verifying correct data output from the end of the scan chain to the scan outputs, and leak testing the scan chain with undetermined states for scan cells in the scan chain.

    摘要翻译: 公开了用于待测仿真设备('DUT')的扫描验证的方法,装置和产品,DUT具有扫描链,扫描输入和扫描输出,其包括验证从DUT的扫描输入的正确数据输入到 扫描链的开始,验证扫描输入和扫描输出之间的扫描链中的扫描数据的正确传播,验证从扫描链的末端输出到扫描输出的正确数据,并对具有未确定状态的扫描链进行泄漏测试 用于扫描链中的扫描单元。

    Scan verification for a device under test
    3.
    发明申请
    Scan verification for a device under test 有权
    对被测设备进行扫描验证

    公开(公告)号:US20070061644A1

    公开(公告)日:2007-03-15

    申请号:US11206846

    申请日:2005-08-18

    IPC分类号: G01R31/28

    CPC分类号: G01R31/318583

    摘要: Methods, apparatus, and products are disclosed for scan verification for a simulated device under test (‘DUT’), the DUT having scan chains, scan inputs, and scan outputs that include verifying correct data entry from the scan inputs of the DUT into the beginning of the scan chain, verifying correct propagation of scan data in the scan chain between the scan inputs and the scan outputs, verifying correct data output from the end of the scan chain to the scan outputs, and leak testing the scan chain with undetermined states for scan cells in the scan chain.

    摘要翻译: 公开了用于待测仿真设备('DUT')的扫描验证的方法,装置和产品,DUT具有扫描链,扫描输入和扫描输出,其包括验证从DUT的扫描输入的正确数据输入到 扫描链的开始,验证扫描输入和扫描输出之间的扫描链中的扫描数据的正确传播,验证从扫描链的末端输出到扫描输出的正确数据,并对具有未确定状态的扫描链进行泄漏测试 用于扫描链中的扫描单元。