公开(公告)号：US06173019B2

公开(公告)日：2001-01-09

申请号：US09076183

申请日：1998-05-12

申请人： Wong Hee ,  Abhijit Phanse

发明人： Wong Hee ,  Abhijit Phanse

IPC分类号： H04L2506

CPC分类号： H04L25/06 ,  H04L25/03885

摘要： A closed feedback loop controls the baseline correction of a data signal. Detected signal information about the baseline and positive and negative peaks of the incoming data signal is processed to generate a baseline correction signal which identifies the difference, if any, between the present data signal baseline and that which is desired. This baseline correction signal is summed with the original data signal to bring its baseline into conformance with the desired baseline.

摘要翻译： 闭合反馈环路控制数据信号的基线校正。 处理关于输入数据信号的基线和正峰值和负峰值的检测信号信息，以产生基线校正信号，其识别当前数据信号基线与期望的基线之间的差异（如果有的话）。 该基线校正信号与原始数据信号相加，使其基线与期望的基线一致。

公开(公告)号：US6043766A

公开(公告)日：2000-03-28

申请号：US76187

申请日：1998-05-12

申请人： Wong Hee ,  Abhijit Phanse

发明人： Wong Hee ,  Abhijit Phanse

IPC分类号： H03M1/12

CPC分类号： H03M1/12

摘要： A distributive encoder for receiving and processing digital error signals representing variations in peak values of an equalized incoming digital data signal and in accordance therewith encoding error signals which represent signal peak errors in data signals for purposes of identifying erroneous signal baseline, peak and equalization conditions. The digital error signals represent variations in peak values of an equalized incoming digital data signal which includes a data signal baseline intermediate to its positive and negative peaks. Two sets of the digital error signals identify when present positive and negative levels transcend prior positive and negative levels, respectively, of the equalized incoming digital data signal. Using various subsets of these digital error signals, the distributive encoder generates encoded error signals which identify erroneous signal baseline, peak and equalization conditions. Using various ones of these encoded error signals, a baseline control circuit can generate a baseline control signal for use in controlling a correction of the equalized incoming digital data signal baseline, a peak control circuit can generate a peak control signal for use in controlling compensation for the positive and negative peaks of the equalized incoming digital data signal, and an equalization control circuit can generate a set of equalization control signals for use in controlling the equalization of the incoming digital data signal.

摘要翻译： 一种分配编码器，用于接收和处理表示均衡输入数字数据信号的峰值变化的数字误差信号，并根据编码误差信号，代表数据信号中的信号峰值误差，以识别错误的信号基线，峰值和均衡条件。 数字误差信号表示均衡输入数字数据信号的峰值的变化，其包括在其正峰值和负峰值之间的数据信号基线。 两组数字误差信号识别当存在正和负电平分别超过均衡输入数字数据信号的先前正和负电平时。 使用这些数字误差信号的各种子集，分布式编码器产生识别错误信号基线，峰值和均衡条件的编码误差信号。 使用这些编码的误差信号中的各种，基线控制电路可以产生用于控制均衡的输入数字数据信号基线的校正的基线控制信号，峰值控制电路可以产生用于控制补偿的峰值控制信号 均衡输入数字数据信号的正和负峰值以及均衡控制电路可以产生用于控制输入数字数据信号的均衡的一组均衡控制信号。