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公开(公告)号：US09043514B2
公开(公告)日：2015-05-26
申请号：US14011264
申请日：2013-08-27
发明人： Yuji Yoshida
CPC分类号： G06F5/14 , H04N1/2129 , H04N5/04 , H04N5/0736 , H04N5/23229 , H04N7/18
摘要： A transfer control circuit stores data in a FIFO memory, outputs data in the FIFO memory in response to a data request signal, and outputs a state signal in accordance with an amount of stored data in the FIFO memory. An output data generating unit outputs image data having a horizontal image size in accordance with a horizontal count value and a horizontal synchronizing signal, and thereafter, outputs blank data. When the state signal indicates that the FIFO memory is in a “EMPTY” or “MODERATE” storage state, a blank control unit outputs a blank addition signal until the FIFO memory changes to a “FULL” storage state.
摘要翻译： 传送控制电路将数据存储在FIFO存储器中，响应于数据请求信号输出FIFO存储器中的数据，并根据FIFO存储器中存储的数据量输出状态信号。 输出数据生成单元根据水平计数值和水平同步信号输出具有水平图像尺寸的图像数据，然后输出空白数据。 当状态信号指示FIFO存储器处于“空”或“等待”存储状态时，空白控制单元输出空白加法信号，直到FIFO存储器变为“满”存储状态。
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52.发明授权公开(公告)号：US08908719B2
公开(公告)日：2014-12-09
申请号：US13713017
申请日：2012-12-13
发明人： Jung-Fu Liao , Hung-Chi Huang
CPC分类号： H04L41/08 , G06F5/06 , G06F5/12 , G06F13/40 , G06F2205/061 , H04J3/0635 , H04L41/0816 , H04N5/0736
摘要： An exemplary embodiment of the present disclosure illustrates a clock rate control method. Firstly, a usage of a first input first output (FIFO) buffer in an electronic device is detected. Then, whether the usage falls within a first specific interval is determined, wherein the first specific interval has a first upper limit value and a first lower limit value. When the usage is larger than the first upper limit value, a clock rate of the inner device of the electronic device is increased; when the usage is less than the first lower limit value, the clock rate is decreased.
摘要翻译： 本公开的示例性实施例示出了时钟速率控制方法。 首先，检测电子设备中的第一输入第一输出（FIFO）缓冲器的使用。 然后，确定使用是否在第一特定间隔内，其中第一特定间隔具有第一上限值和第一下限值。 当使用量大于第一上限值时，电子设备的内部设备的时钟速率增加; 当使用量小于第一下限值时，时钟速率降低。
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公开(公告)号：US20140079368A1
公开(公告)日：2014-03-20
申请号：US14115967
申请日：2013-03-08
发明人： Taiji Sasaki , Toshihiko Munetsugu , Yoshimi Nishii , Yuka Ozawa , Takuji Hiramoto , Yoshihiro Ujiie , Tomoki Ogawa
IPC分类号： H04N5/073
CPC分类号： H04N5/0736 , H04N21/4307 , H04N21/4331 , H04N21/4622 , H04N21/6125
摘要： A display device comprising: a reception unit; a display unit; a storage unit; and an acquisition unit. The reception unit receives a stream containing a plurality of video frames and first display timing information specifying a display timing of each video frame. The display unit displays each video frame at a corresponding display timing specified by the first display timing information. The storage unit stores an image and second display timing information specifying a display timing of the image. The acquisition unit acquires correction information specifying a correction amount for correcting the display timing of the image and thereby enabling the image to be displayed in synchronization with the video frames displayed by the display unit. The display unit further displays the image at a corrected display timing determined by correcting the display timing of the image by using the correction amount specified by the correction information.
摘要翻译： 一种显示装置，包括：接收单元; 显示单元; 存储单元; 和收购单位。 接收单元接收包含多个视频帧的流和指定每个视频帧的显示定时的第一显示定时信息。 显示单元以由第一显示定时信息指定的相应显示定时显示每个视频帧。 存储单元存储指定图像的显示定时的图像和第二显示定时信息。 获取单元获取指定用于校正图像的显示定时的校正量的校正信息，从而使得能够与由显示单元显示的视频帧同步地显示图像。 显示单元通过使用由校正信息指定的校正量来校正图像的显示定时而确定的校正显示定时进一步显示图像。
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54.发明申请公开(公告)号：US20130170369A1
公开(公告)日：2013-07-04
申请号：US13713017
申请日：2012-12-13
发明人： JUNG-FU LIAO , HUNG-CHI HUANG
IPC分类号： H04L12/24
CPC分类号： H04L41/08 , G06F5/06 , G06F5/12 , G06F13/40 , G06F2205/061 , H04J3/0635 , H04L41/0816 , H04N5/0736
摘要： An exemplary embodiment of the present disclosure illustrates a clock rate control method. Firstly, a usage of a first input first output (FIFO) buffer in an electronic device is detected. Then, whether the usage falls within a first specific interval is determined, wherein the first specific interval has a first upper limit value and a first lower limit value. When the usage is larger than the first upper limit value, a clock rate of the inner device of the electronic device is increased; when the usage is less than the first lower limit value, the clock rate is decreased.
摘要翻译： 本公开的示例性实施例示出了时钟速率控制方法。 首先，检测电子设备中的第一输入第一输出（FIFO）缓冲器的使用。 然后，确定使用是否在第一特定间隔内，其中第一特定间隔具有第一上限值和第一下限值。 当使用量大于第一上限值时，电子设备的内部设备的时钟速率增加; 当使用量小于第一下限值时，时钟速率降低。
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55.发明授权公开(公告)号：US08072539B1
公开(公告)日：2011-12-06
申请号：US11256502
申请日：2005-10-21
申请人： J. Carl Cooper , Howard Loveless , David Wallen , Mirko Vojnovic
发明人： J. Carl Cooper , Howard Loveless , David Wallen , Mirko Vojnovic
CPC分类号： H04N5/0736 , H04N9/475
摘要： This invention is an apparatus and method for digital processing of television like signals and in particular the use of oversampling and interpolation to achieve improved resolution of the digital version of such signals as compared to a digital version obtained by the use of simple A/D conversion or processing at the desired sample rate. The preferred embodiment utilizes oversampling, interpolation and various filtering in recursive and nonrecursive form to provide output video signals wherein the artifacts and distortion of the video are kept to low levels.
摘要翻译： 本发明是一种用于数字处理电视机信号的装置和方法，特别是使用过采样和内插来实现与通过使用简单的A / D转换获得的数字版本相比，这种信号的数字版本的分辨率得到改善 或以所需的采样率进行处理。 优选实施例利用递归和非递归形式的过采样，内插和各种滤波来提供输出视频信号，其中视频的伪像和失真保持在低电平。
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56.发明申请公开(公告)号：US20100299711A1
公开(公告)日：2010-11-25
申请号：US12679950
申请日：2008-09-19
申请人： Ulrich Kabatek
发明人： Ulrich Kabatek
CPC分类号： H04N5/0736
摘要： A method and a device for synchronizing an image display, a first image signal being provided by a first device and a second image being provided by a second device being brought together for display, the first device and the second device being time-controlled independently of each other. The second image signal is synchronized with the first image signal by modifying a blanking interval of the second image signal.
摘要翻译： 一种用于同步图像显示的方法和装置，由第一装置提供的第一图像信号和由第二装置提供的第二图像被聚集在一起用于显示，第一装置和第二装置被独立于时间控制 彼此。 通过修改第二图像信号的消隐间隔，第二图像信号与第一图像信号同步。
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公开(公告)号：US07817191B2
公开(公告)日：2010-10-19
申请号：US11821473
申请日：2007-06-21
申请人： Ronald Norman Prusia
发明人： Ronald Norman Prusia
IPC分类号： H04N5/76
CPC分类号： H04N5/23203 , H04J3/062 , H04J3/07 , H04L25/03343 , H04N5/0736
摘要： An apparatus and method for use in transmitting data that is supplied with a high jitter input clock in a serial data stream over a single fiber cable. Video data from a camera is stored in memory using the high jitter clock. A stable clock is used to transmit the data from memory. To account for drift between the input clock and the stable clock idle words are added to or deleted from the transmitted data.
摘要翻译： 一种用于在单个光纤电缆上传输在串行数据流中提供有高抖动输入时钟的数据的装置和方法。 使用高抖动时钟将摄像机的视频数据存储在存储器中。 使用稳定的时钟从存储器传输数据。 为了解决输入时钟和稳定时钟之间的漂移，空闲字被添加到发送数据或从发送的数据中删除。
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公开(公告)号：US20090040394A1
公开(公告)日：2009-02-12
申请号：US11574458
申请日：2005-08-31
IPC分类号： H04N9/31
CPC分类号： H04N5/0736 , H04N5/2624 , H04N9/3147
摘要： The invention relates to an image processing device (1, 48, 51) including: several image signal inputs (2-9) for receiving a respective image input signal, the signals being unsynchronized; at least one image signal output (23-26) for emitting at least one image output signal; a combiner (22) for combining the different image input signals to form the image output signal; several synchronizers (14-21), which are respectively connected downstream of the image signal inputs (2-9) and which synchronize the unsynchronized image input signals; and several distorters or rectifiers for distorting or rectifying the individual image input signals before they are combined to form the image output signal. According to the invention, the distorters or rectifiers are formed by the individual synchronizers (14-21) and the image input signals are distorted or rectified independently of one another by one or more synchronizers (14-21). The invention also relates to an associated operating method.
摘要翻译： 本发明涉及一种图像处理装置（1，48，51），包括：几个图像信号输入（2-9），用于接收相应的图像输入信号，所述信号是不同步的; 至少一个用于发射至少一个图像输出信号的图像信号输出（23-26）; 组合器（22），用于组合不同的图像输入信号以形成图像输出信号; 多个同步器（14-21），其分别连接在图像信号输入（2-9）的下游，并且使不同步的图像输入信号同步; 以及用于在将各个图像输入信号组合之前使各个图像输入信号变形或整流以形成图像输出信号的多个变干器或整流器。 根据本发明，变形器或整流器由单独的同步器（14-21）形成，并且图像输入信号通过一个或多个同步器（14-21）彼此独立地失真或整流。 本发明还涉及一种相关联的操作方法。
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59.发明申请Frame synchronizer, optical disk device, information recording/reproducing apparatus, and signal synchronizing method 审中-公开帧同步器，光盘装置，信息记录/再现装置和信号同步方法公开(公告)号：US20060132651A1
公开(公告)日：2006-06-22
申请号：US11280251
申请日：2005-11-17
申请人： Ko Matsushima
发明人： Ko Matsushima
IPC分类号： H04N9/475
CPC分类号： H04N21/4307 , H04N5/0736
摘要： To provide a frame synchronizer free of any loss of additional information added to frame data of an input video signal. An embodiment of the invention relates to a frame synchronizer for receiving a video signal having a first synchronization signal and frame data on a frame basis, writing the frame data to a memory on the frame basis in accordance with the first synchronization signal, and reading the frame data from the memory on the frame basis in accordance with a second synchronization signal of a frequency different from a frequency of the first synchronization signal to output the frame data, including: a synchronization signal generator generating the second synchronization signal having the frequency higher than a preset standard frequency. With such a configuration, it is possible to prevent the loss of the additional information added to the frame data in the input video data.
摘要翻译： 为了提供帧同步器，没有任何丢失添加到输入视频信号的帧数据的附加信息。 本发明的实施例涉及一种帧同步器，用于在帧基础上接收具有第一同步信号和帧数据的视频信号，根据第一同步信号将帧数据写入存储器，并读取 根据与第一同步信号的频率不同的频率的第二同步信号，基于帧从存储器读取帧数据，以输出帧数据，包括：同步信号发生器，生成频率高于 预设的标准频率。 通过这样的配置，可以防止在输入的视频数据中添加到帧数据中的附加信息的丢失。
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公开(公告)号：US20040068588A1
公开(公告)日：2004-04-08
申请号：US10635071
申请日：2003-08-06
IPC分类号： G06F015/16
CPC分类号： H04N5/0736 , H04J3/0632 , H04J3/0638 , H04N21/4305 , H04N21/43615
摘要： A method of synchronizing a multimedia content stream for output to a plurality of wired and wireless output device in a network having plural realms, wherein each realm includes a CTL, includes buffering the multimedia content stream in a first realm; determining a buffer delay; transmitting the buffer delay to all CTLs in all realms of the network; and transmitting the multimedia content stream to all realms in the network.
摘要翻译： 一种在具有多个领域的网络中同步用于输出的多媒体内容流到多个有线和无线输出设备的方法，其中每个领域包括CTL，包括在第一领域中缓冲多媒体内容流; 确定缓冲区延迟; 将所述缓冲器延迟发送到所述网络的所有领域中的所有CTL; 并将多媒体内容流发送到网络中的所有领域。
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