公开(公告)号：US20230053953A1

公开(公告)日：2023-02-23

申请号：US17434543

申请日：2020-05-12

申请人： ENKRIS SEMICONDUCTOR, INC.

发明人： Kai CHENG ,  Weihua LIU

IPC分类号： H01L21/02 ,  H01L33/00

摘要： A group-III-nitride structure and a manufacturing method thereof are provided. In the manufacturing method, one or more grooves are formed by etching a first group-III-nitride epitaxial layer with a patterned first mask layer as a mask; then a second mask layer is formed at least on one or more bottom walls of the one or more grooves, and a first epitaxial growth is performed on the first group-III-nitride epitaxial layer to laterally grow and form a second group-III-nitride epitaxial layer with the second mask layer as a mask, where the one or more grooves are filled with the second group III-nitride epitaxial layer; a second epitaxial growth is then performed on the second group-III-nitride epitaxial layer to grow and form a third group-III-nitride epitaxial layer on the second group-III-nitride epitaxial layer and the patterned first mask layer.

公开(公告)号：US20230015133A1

公开(公告)日：2023-01-19

申请号：US17783382

申请日：2020-06-03

申请人： ENKRIS SEMICONDUCTOR, INC.

发明人： Kai Cheng ,  Dandan Zhu

IPC分类号： H01L29/66 ,  H01L29/778 ,  H01L21/223 ,  H01L29/06

摘要： Provided are a semi-conductor structure and a manufacturing method thereof. The semi-conductor structure includes: a substrate, a heterojunction, a P-type ion doped layer and a gate insulation layer disposed from bottom to top, wherein the heterojunction includes a source region, a drain region and a gate region; the P-type ion doped layer in the gate region includes an activated region and non-activated regions, P-type doping ions in the activated region are activated, and P-type doping ions in the non-activated regions are passivated; the non-activated regions include at least two regions which are spaced apart in a direction perpendicular to a connection line of the source region and the drain region; the gate insulation layer is located on the non-activated region to expose the activated region.

公开(公告)号：US11424352B2

公开(公告)日：2022-08-23

申请号：US16819533

申请日：2020-03-16

申请人： ENKRIS SEMICONDUCTOR, INC.

发明人： Kai Cheng

IPC分类号： H01L29/66 ,  H01L29/778 ,  H01L29/20

摘要： The present application provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes a channel layer, a barrier layer located on the channel layer, a composition change layer located on the barrier layer, and a p-type semiconductor material layer located in the gate region of the composition change layer, wherein a gate region is defined on a surface of the composition change layer, and a material of the composition change layer includes at least one composition change element.

公开(公告)号：US20220246752A1

公开(公告)日：2022-08-04

申请号：US17613575

申请日：2019-07-29

申请人： ENKRIS SEMICONDUCTOR, INC.

发明人： Kai Cheng

IPC分类号： H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/423 ,  H01L29/40 ,  H01L29/66

摘要： The present application provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a first n-type semiconductor layer, a p-type semiconductor layer, and a second n-type semiconductor layer which are stacked. A buried layer made of AlGaN is disposed in the first n-type semiconductor layer. A trench at least penetrates through the second n-type semiconductor layer and the p-type semiconductor layer. At least part of the buried layer is reserved below the trench. A gate electrode is in the trench. The method is used to manufacture this semiconductor structure.

公开(公告)号：US20220115525A1

公开(公告)日：2022-04-14

申请号：US17263133

申请日：2019-11-26

申请人： ENKRIS SEMICONDUCTOR, INC.

发明人： Kai CHENG

IPC分类号： H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66

摘要： A semiconductor structure, comprising: a semiconductor substrate, a heterojunction, an in-situ insulating layer and a transition layer, which are arranged in sequence from bottom to top; a groove, passing through the in-situ insulating layer and the transition layer; and a P-type semiconductor layer, disposed in the groove and in a gate region on the transition layer, wherein the P-type semiconductor layer does not fully fill the groove. A method of manufacturing semiconductor structure is further disclosed.

公开(公告)号：US20220102530A1

公开(公告)日：2022-03-31

申请号：US17526321

申请日：2021-11-15

申请人： ENKRIS SEMICONDUCTOR, INC.

发明人： Kai CHENG

IPC分类号： H01L29/66 ,  H01L29/20 ,  H01L29/778

摘要： According to the preparation method for a semiconductor structure provided in the present application, a selective epitaxial growth method is used, without etching the n-type semiconductor layer and the p-type semiconductor layer, thus avoiding problems such as uncontrollable etching depth and damaged etched surface, which effectively reduces gate leakage, maintains low resistance in a channel region, suppresses current collapse, and improves reliability and stability of a device.

公开(公告)号：US20220085195A1

公开(公告)日：2022-03-17

申请号：US17535934

申请日：2021-11-26

申请人： ENKRIS SEMICONDUCTOR, INC.

发明人： Kai CHENG

IPC分类号： H01L29/778 ,  H01L29/20 ,  H01L29/66

摘要： Disclosed are a semiconductor structure and a preparing method for a semiconductor structure, which relate to the technical field of microelectronics. The semiconductor structure includes a buffer layer including a diffusion element; a diffusion blocking layer formed on the buffer layer, the diffusion blocking layer including an adsorptive element; and a channel layer formed on the diffusion blocking layer. In this embodiment, the diffusion blocking layer is provided with an adsorptive element that adsorbs the diffusion element, so as to effectively block the diffusion of the diffusion element to the channel layer from the buffer layer. In addition, a change in the composition of the adsorptive element in the diffusion blocking layer is provided to avoid stress release of the diffusion blocking layer.

公开(公告)号：US20210384341A1

公开(公告)日：2021-12-09

申请号：US17409419

申请日：2021-08-23

申请人： Yu ZHU ,  ENKRIS SEMICONDUCTOR, INC.

发明人： Kai CHENG ,  Yu ZHU

IPC分类号： H01L29/778 ,  H01L29/20 ,  H01L29/66 ,  H01L29/78

摘要： Disclosed are a semiconductor structure and a manufacturing method therefor, solving the problem that it is difficult for an existing semiconductor structure to deplete a carrier concentration of a channel under a gate so as to achieve an enhancement-mode device. The semiconductor structure comprises: a channel layer and a barrier layer stacked in sequence. A gate region is defined on a surface of the barrier layer; a plurality of trenches formed in the gate region. The plurality of trenches are extended into the channel layer; and a stress applying material filled in the plurality of trenches. A lattice constant of the stress applying material is greater than that of the channel layer.

公开(公告)号：US20210193794A1

公开(公告)日：2021-06-24

申请号：US17195893

申请日：2021-03-09

申请人： ENKRIS SEMICONDUCTOR, INC.

发明人： Kai CHENG ,  Kai LIU

IPC分类号： H01L29/06 ,  H01L29/207

摘要： The present invention provides a semiconductor structure and a preparation method thereof. A transition metal and an impurity are co-doped on a buffer layer above a substrate layer to reduce the leakage current of a semiconductor device, to improve the pinch-off behavior, and to avoid the device current collapse, moreover, the ranges of the concentration of the transition metal and the impurity in the buffer layer are controlled to ensure the balance of the leakage current during the dynamic characteristics of the device.

公开(公告)号：US20210143264A1

公开(公告)日：2021-05-13

申请号：US17151211

申请日：2021-01-18

申请人： ENKRIS SEMICONDUCTOR, INC.

发明人： Kai CHENG

IPC分类号： H01L29/66 ,  H01L21/324 ,  H01L29/778 ,  H01L29/43

摘要： The present application provides a method for preparing a p-type semiconductor structure, an enhancement mode device and a method for manufacturing the same. The method for preparing a p-type semiconductor structure includes: preparing a p-type semiconductor layer; preparing a protective layer on the p-type semiconductor layer, in which the protective layer is made of AlN or AlGaN; and annealing the p-type semiconductor layer under protection of the protective layer, and at least one of the p-type semiconductor layer and the protective layer is formed by in-situ growth. In this way, the protective layer can protect the p-type semiconductor layer from volatilization and to form high-quality surface morphology in the subsequent high-temperature annealing treatment of the p-type semiconductor layer.