公开(公告)号：US20070219658A1

公开(公告)日：2007-09-20

申请号：US11377538

申请日：2006-03-16

Applicant: Sumit Kumar

Inventor： Sumit Kumar

IPC: G06F19/00

CPC classification number: F15B13/0814

Abstract: A method for automating the manifold design process based on a hydraulic circuit cavity geometry and manifold design parameters successively merges stored design patterns, including orientations and connectivity data of each cavity into an evolving manifold topology. Cross-drill connections are added to the topology. A complete 3-D manifold model is then exported through a CAD program.

Abstract translation: 基于液压回路腔体几何形状和歧管设计参数使歧管设计过程自动化的方法将存储的设计模式（包括每个空腔的取向和连通性数据）合并到演进的歧管拓扑中。 拓扑连接被添加到拓扑中。 然后通过CAD程序导出完整的3-D歧管模型。

公开(公告)号：US07248664B2

公开(公告)日：2007-07-24

申请号：US10671872

申请日：2003-09-29

Applicant: Douglas Fast ,  Surinder Kumar ,  Sumit Kumar

Inventor： Douglas Fast ,  Surinder Kumar ,  Sumit Kumar

IPC: H03D3/24

CPC classification number: H03L7/093 ,  H03L7/0994 ,  H03L7/10 ,  H03L2207/50

Abstract: A time-sliced discrete-time Phase Locked Loop which is suitable for simultaneously synchronizing multiple input signals to multiple output signals is provided by implementing a discrete-time phase detector, loop filter, and voltage controlled oscillator that together operate as a single discrete-time PLL in hardware and applying control logic to retrieve the history for each signal pair from a context memory (RAM), to enable the discrete-time PLL hardware, and to store the resulting history in the context memory for use in subsequent operations for a particular input/output signal pair.

Abstract translation: 通过实现离散时间相位检测器，环路滤波器和压控振荡器来提供适合于将多个输入信号同时同步到多个输出信号的时间分离的离散时间锁相环，其一起作为单个离散时间 PLL在硬件中并且应用控制逻辑来从上下文存储器（RAM）中检索每个信号对的历史，以实现离散时间PLL硬件，并将所得到的历史存储在上下文存储器中，以用于特定的后续操作 输入/输出信号对。