公开(公告)号：US11949424B2

公开(公告)日：2024-04-02

申请号：US17743902

申请日：2022-05-13

申请人： SHENZHEN ZHONCENT TECHNOLOGIES CO., LTD.

发明人： Zhi Quan

IPC分类号： H03L7/099 ,  H03L7/085 ,  H03L7/197

CPC分类号： H03L7/099 ,  H03L7/085 ,  H03L7/1974 ,  H03L2207/50

摘要： The present disclosure provide a device, method and storage medium for frequency calibration for voltage-controlled oscillators. The device includes: A frequency divider connected with a VCO, a time-digital converter connected with the frequency divider, a logic controller connected with the time-digital converter, a digital-to-analog converter connected with the voltage-controlled oscillator; The frequency divider is used to divide the signal generated by the voltage-controlled oscillator into N times to get the frequency divider signal; Time-digital converter is used to measure the actual time period of frequency division signal; And the logic controller is used to generate the control voltage according to the difference between the actual time period of the frequency division signal and the calibration period of the frequency division signal, and adjust the frequency of the VCO according to the control voltage. The frequency precision of VCO is improved and the model-free adaptive frequency calibration of VCO is realized.

公开(公告)号：US20230387925A1

公开(公告)日：2023-11-30

申请号：US18321017

申请日：2023-05-22

申请人： Univ. Electronic Science and Technology of China

发明人： Zheng WANG ,  Xinlin GENG ,  Zonglin YE ,  Yao XIAO ,  Qian XIE

IPC分类号： H03L7/197 ,  H03L7/093

CPC分类号： H03L7/1974 ,  H03L7/093 ,  H03L2207/50

摘要： The disclosure relates to mixed analog-digital circuits, and more specifically a low-noise millimeter-wave fractional-N frequency synthesizer. It overcomes quantization noise and fractional spurs caused by the limited dynamic range and nonlinearity of time error amplifiers (TA) in traditional phase-locked loop structures based on TA. In addition to the traditional structure, the synthesizer includes a coarse digital-to-time converter (CDTC), a fine digital-to-time converter (FDTC), and DTC non-linearity calibration circuits. By inserting the CDTC and FDTC before and after the TA, respectively, the variance of the input phase difference of the TA can be reduced, thereby improving the TA linearity and suppressing the quantization noise and spur generated by fractional-N operation. Furthermore, by using non-linearity calibration, the non-linearity of DTC and TA can be compensated to avoid large quantization noise and spur while the second order quantization noise reshaping is maintained. Furthermore, a high-gain TA can increase the resolution of the FDTC.

公开(公告)号：US11705914B2

公开(公告)日：2023-07-18

申请号：US17454221

申请日：2021-11-09

申请人： Analog Devices, Inc.

发明人： Reuben P. Nelson

IPC分类号： H03L7/08 ,  H03L7/107 ,  G06F1/12 ,  G06F1/10 ,  H04B1/16 ,  H03K5/00

CPC分类号： H03L7/1075 ,  G06F1/10 ,  G06F1/12 ,  H03L7/0807 ,  H03K2005/00143 ,  H03L2207/50 ,  H04B1/16

摘要： Apparatus and methods for clock synchronization and frequency translation are provided herein. Clock synchronization and frequency translation integrated circuits (ICs) generate one or more output clock signals having a controlled timing relationship with respect to one or more reference signals. The teachings herein provide a number of improvements to clock synchronization and frequency translation ICs, including, but not limited to, reduction of system clock error, reduced variation in clock propagation delay, lower latency monitoring of reference signals, precision timing distribution and recovery, extrapolation of timing events for enhanced phase-locked loop (PLL) update rate, fast PLL locking, improved reference signal phase shift detection, enhanced phase offset detection between reference signals, and/or alignment to phase information lost in decimation.

公开(公告)号：US20190253058A1

公开(公告)日：2019-08-15

申请号：US16329312

申请日：2016-09-29

申请人： INTEL IP CORPORATION

发明人： Ashoke Ravi ,  Rotem Banin ,  Ofir Degani ,  David Ben-Haim ,  Yigal Kalmanovich

IPC分类号： H03L7/099 ,  H03L7/093 ,  H04L7/08 ,  H04L7/033

CPC分类号： H03L7/0995 ,  H03L7/093 ,  H03L2207/50 ,  H04L7/0331 ,  H04L7/08

摘要： For example, a digital PLL may include a digitally controlled Ring Oscillator (DCRO) configured to generate a frequency output based on a control signal, the DCRO comprising a plurality of stages in a cyclic order, a first stage of the plurality of stages comprising a plurality of inverter modules controlled by the control signal and comprising a plurality of outputs that drive inputs of a plurality of second stages in the plurality of stages; a decoder to decode a phase of the DCRO based on a plurality of sampled phases of the plurality of stages of the DCRO; and a phase error estimator to estimate a phase error based on the phase of the DCRO and a frequency control word, the control signal is based on the phase error.

公开(公告)号：US20190074842A1

公开(公告)日：2019-03-07

申请号：US16084997

申请日：2017-03-15

申请人： BOARD OF REGENTS, THE UNIVERSITY OF TEXAS SYSTEM

发明人： Nan Sun

IPC分类号： H03L7/197 ,  H03L7/089 ,  H03L7/091 ,  H03L7/093

CPC分类号： H03L7/1974 ,  H03L7/06 ,  H03L7/089 ,  H03L7/091 ,  H03L7/093 ,  H03L7/18 ,  H03L7/197 ,  H03L2207/50

摘要： The exemplified technology provides a circuit and clock synthesis technique that suppresses quantization noise in a ΔΣ fractional-N phase-locked loop (PLL) using a fineresolution multi-element fractional divider. The circuit and clock synthesis method beneficially suppresses noise uniformly over the entire frequency range. The circuit can be implemented using mostly digital circuitry, and is applicable for use with both analog and digital PLLs. With an 8-element fractional divider, it is observed that the circuit and clock synthesis technique can suppress quantization noise while incurring only a small increase in hardware complexity.

公开(公告)号：US20190052281A1

公开(公告)日：2019-02-14

申请号：US15674985

申请日：2017-08-11

申请人： Analog Devices Global

发明人： Frederick Carnegie Thompson ,  Varun Agrawal ,  Jose Barreiro Silva ,  Declan M. Dalton

IPC分类号： H03M1/08 ,  H03M1/74 ,  H03M1/06 ,  H03M1/12 ,  H03L7/089 ,  H03K5/1252 ,  H03K7/06 ,  H04L27/06

CPC分类号： H03M1/0836 ,  H03K5/1252 ,  H03K7/06 ,  H03L7/08 ,  H03L7/0893 ,  H03L2207/50 ,  H03M1/0621 ,  H03M1/1245 ,  H03M1/747 ,  H03M3/43 ,  H03M3/458 ,  H04L27/066

摘要： This disclosure relates to data converters for electronic systems. An example system includes a primary analog to digital converter (ADC) circuit, a slope calculation circuit, a digital phase lock loop (DPLL) circuit, a sampling error circuit, and a summing circuit. The primary ADC circuit samples an input signal and produces a digital output signal representative of the input signal. The slope calculation circuit generates a digital slope signal representative of slope of the input signal, and the DPLL circuit provides a sampling clock signal to the primary ADC circuit. The sampling error circuit generates a sampling error signal representative of sampling error by the primary ADC circuit using the digital slope signal and the sampling clock signal. The summing circuit receives the sampling error signal and the digital output signal of the primary ADC circuit and generates an adjusted digital output signal representative of the input signal.

公开(公告)号：US20180351508A1

公开(公告)日：2018-12-06

申请号：US15808132

申请日：2017-11-09

申请人： SK hynix Inc.

发明人： Min Soon HWANG

IPC分类号： H03B5/04 ,  H03L7/099 ,  H03L7/091 ,  H03K19/094 ,  H03M1/66

CPC分类号： H03K3/0315 ,  H03K3/011 ,  H03K19/09425 ,  H03L7/0991 ,  H03L7/0995 ,  H03L2207/50 ,  H03M1/745

摘要： Disclosed is an oscillator including: a digital to analog converter configured to convert a received control code into an analog voltage and output the converted analog voltage; a mirror circuit configured to adjust a current of a common output node to which the analog voltage is applied; and a periodic signal output circuit configured to output a periodic signal having a frequency according to the analog voltage, in which the digital to analog converter, the mirror circuit, and the periodic signal output circuit are implemented with tri-state inverters.

公开(公告)号：US10063368B2

公开(公告)日：2018-08-28

申请号：US15642571

申请日：2017-07-06

申请人： R.F. Architecture Co., Ltd.

发明人： Shinichi Morisaka

IPC分类号： H03D3/24 ,  H04L7/033 ,  H04B1/40 ,  H03L7/091 ,  H03L7/099

CPC分类号： H04L7/0331 ,  H03B21/01 ,  H03L7/06 ,  H03L7/091 ,  H03L7/099 ,  H03L7/16 ,  H03L7/185 ,  H03L2207/50 ,  H04B1/40 ,  H04B1/403 ,  H04L5/0007 ,  H04L27/00 ,  H04L2027/0024 ,  H04L2027/0026 ,  H04L2027/0053 ,  H04L2027/0065

摘要： A phase locked loop circuit that is capable of stabilizing a frequency of an input signal even in the case where the frequency is unstable is provided. The phase locked loop circuit that corrects a frequency error of an output signal from an oscillator to a predetermined target frequency; an ADC that converts the output signal to a digital signal; reference frequency output means that outputs a reference frequency signal; frequency error detection means that detects the frequency error based on the digital signal and the reference frequency signal; correction signal generation means that generates an error correction signal based on the frequency error; a DAC that converts the error correction signal to an analog signal; and a multiplier that multiplies the output signal by the analog signal to correct the frequency error of the output signal.

公开(公告)号：US10063243B2

公开(公告)日：2018-08-28

申请号：US15668790

申请日：2017-08-04

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Jingdong Deng ,  Chung S. Ho ,  David Flye ,  Zhenrong Jin ,  Ramana M. Malladi

IPC分类号： H03L7/06 ,  H03L7/087 ,  H03L7/099 ,  G06F17/50

CPC分类号： H03L7/087 ,  G06F17/5045 ,  H03L7/0991 ,  H03L7/0995 ,  H03L7/0997 ,  H03L2207/06 ,  H03L2207/50 ,  H05K999/99

摘要： A phase locked loop circuit is disclosed. The phase locked loop circuit includes a ring oscillator. The phase locked loop circuit also includes a digital path including a digital phase detector. The phase locked loop circuit further includes an analog path including a linear phase detector. Additionally, the phase locked loop circuit includes a feedback path connecting an output of the ring oscillator to an input of the digital path and an input of the analog path. The digital path and the analog path are parallel paths. The digital path provides a digital tuning signal the ring oscillator that digitally controls a frequency of the ring oscillator. The analog path provides an analog tuning signal the ring oscillator that continuously controls the frequency of the ring oscillator.

公开(公告)号：US10003344B2

公开(公告)日：2018-06-19

申请号：US15009405

申请日：2016-01-28

申请人： Cirrus Logic International Semiconductor Ltd.

发明人： John Paul Lesso

IPC分类号： H03L7/099 ,  H03L7/08 ,  H03G5/00 ,  H03L7/087 ,  H03L7/14 ,  H03L7/18 ,  G06F3/16

CPC分类号： H03L7/099 ,  G06F3/162 ,  H03G5/00 ,  H03G5/005 ,  H03L7/08 ,  H03L7/087 ,  H03L7/14 ,  H03L7/18 ,  H03L2207/50

摘要： A clock generator receives first and second clock signals, and input representing a desired frequency ratio. A comparison is made between frequencies of an output clock signal and the first clock signal, and a first error signal represents the difference between the desired frequency ratio and this comparison result. The first error signal is filtered. A comparison is made between frequencies of the output clock signal and the second clock signal, and a second error signal represents the difference between the filtered first error signal and this comparison result. The second error signal is filtered. A numerically controlled oscillator receives the filtered second error signal and generates an output clock signal. As a result, the output clock signal has the jitter characteristics of the first input clock signal over a useful range of jitter frequencies and the frequency accuracy of the second input clock signal.