公开(公告)号：US06353551B1

公开(公告)日：2002-03-05

申请号：US09443940

申请日：1999-11-19

申请人： Andy Lee

发明人： Andy Lee

IPC分类号： G11C1100

CPC分类号： G11C7/20

摘要： A static random access memory (“SRAM”) that is especially suitable for such uses as inclusion on a programmable logic device to provide programmable control of the configuration of that device. The SRAM includes a plurality of SRAM cells, all of which are simultaneously cleared to a first of two logic states by application of a second of the two logic states to clear terminals of the cells. Any cell that needs to be programmed to the second of the two logic states is thereafter specifically addressed and a data signal thereby applied which programs the cell to the second logic state. The cells are preferably constructed so that they are programmed to the second logic state by application of a data signal having the first logic state. Even a very small unipolar MOS pass gate transistor can therefore be used as the addressable path through which the data signal is applied. The memory may also include circuitry for verifying the contents of each cell via the data input terminal of the cell.

摘要翻译： 一种静态随机存取存储器（“SRAM”），其特别适用于包括在可编程逻辑器件上的这种用途，以提供对该器件的配置的可编程控制。 SRAM包括多个SRAM单元，所有这些SRAM单元都通过应用两个逻辑状态中的第二逻辑状态同时被清除为两个逻辑状态中的第一个，以清除单元的端子。 此后需要将任何要编程到两个逻辑状态中的第二个的单元格寻址，并且由此应用数据信号，将该单元编程到第二逻辑状态。 这些单元优选地构造成使得它们通过应用具有第一逻辑状态的数据信号被编程到第二逻辑状态。 因此，即使非常小的单极MOS栅极晶体管也可以用作施加数据信号的寻址路径。 存储器还可以包括用于经由单元的数据输入端验证每个单元的内容的电路。