公开(公告)号：US20240363189A1

公开(公告)日：2024-10-31

申请号：US18471307

申请日：2023-09-21

申请人： SK hynix Inc.

发明人： Young Ook SONG

IPC分类号： G11C29/52 ,  G11C7/10 ,  G11C7/20 ,  G11C7/22

CPC分类号： G11C29/52 ,  G11C7/1069 ,  G11C7/20 ,  G11C7/222

摘要： A memory system includes a plurality of memory devices; and a memory controller configured to perform an initial training operation to set a plurality of time codes corresponding to the plurality of memory devices, respectively, receive a plurality of data signals read from the plurality of memory devices, as internal data signals, according to the plurality of time codes, respectively, and adjust the plurality of time codes based on the internal data signals and error pattern maps generated by collecting error location information for the internal data signals.

公开(公告)号：US20240347085A1

公开(公告)日：2024-10-17

申请号：US18473837

申请日：2023-09-25

申请人： Samsung Electronics Co., Ltd.

发明人： Dongin SEO ,  Jaewoong KIM ,  Changhyun BAE ,  Hyeseung YU

IPC分类号： G11C7/20 ,  G11C7/10 ,  G11C7/22

CPC分类号： G11C7/20 ,  G11C7/106 ,  G11C7/1063 ,  G11C7/222

摘要： A receiver includes a buffer configured to generate an internal data signal by comparing a received data signal with a reference voltage, a decision feedback equalizer configured to generate a sampled signal based on a present value of the internal data signal and on a feedback signal, and configured to provide one of the sampled signal or a first logic level as the feedback signal based on a reset control signal, the sampled signal corresponding to a previous value of the internal data signal, a deserializer configured to generate an output data by deserializing the sampled signal, and a reset control circuit configured to generate the reset control signal based on operating information associated with a write operation of the data signal and configured to provide the reset control signal to the decision feedback equalizer.

公开(公告)号：US20240320080A1

公开(公告)日：2024-09-26

申请号：US18586907

申请日：2024-02-26

申请人： Rambus Inc.

发明人： Thomas J. GIOVANNINI ,  Catherine CHEN ,  Scott C. BEST ,  John Eric LINSTADT ,  Frederick A. WARE

IPC分类号： G06F11/07 ,  G06F13/00 ,  G11C5/04 ,  G11C7/20 ,  G11C8/12 ,  G11C29/26 ,  G11C29/44

CPC分类号： G06F11/079 ,  G06F11/073 ,  G06F11/0772 ,  G06F13/00 ,  G11C5/04 ,  G11C7/20 ,  G11C8/12 ,  G11C29/26 ,  G11C29/44

摘要： During system initialization, each data buffer device and/or memory device on a memory module is configured with a unique (at least to the module) device identification number. In order to access a single device (rather than multiple buffers and/or memory devices), a target identification number is written to all of the devices using a command bus connected to all of the data buffer devices or memory devices, respectively. The devices whose respective device identification numbers do not match the target identification number are configured to ignore future command bus transactions (at least until the debug mode is turned off.) The selected device that is configured with a device identification number matching the target identification number is configured to respond to command bus transactions.

公开(公告)号：US12100472B2

公开(公告)日：2024-09-24

申请号：US17993635

申请日：2022-11-23

申请人： SK hynix Inc.

发明人： Jun Seok Noh ,  Byeong Yong Go ,  Sang Woo Yoon ,  No Geun Joo

IPC分类号： G11C7/20 ,  G11C7/10 ,  G11C7/22

CPC分类号： G11C7/109 ,  G11C7/1093 ,  G11C7/20 ,  G11C7/22

摘要： An integrated circuit includes a sampling control circuit configured to generate a sampling enable signal by dividing a sampling period into a plurality of sub-sections according to an active counting signal generated by counting a number of inputs of an active signal during the sampling period, and comparing the active counting signal with a random signal for each sub-section; and a sampling circuit configured to sample and store an input address according to the sampling enable signal.

公开(公告)号：US12086015B2

公开(公告)日：2024-09-10

申请号：US17575334

申请日：2022-01-13

申请人： Micron Technology, Inc.

发明人： Matthew David Rowley

IPC分类号： G11C16/26 ,  G06F1/3296 ,  G06F12/02 ,  G11C5/14 ,  G11C7/10 ,  G11C7/20 ,  G11C7/22 ,  G11C16/30 ,  H10B41/30 ,  H10B41/40 ,  G06F1/3234

CPC分类号： G06F1/3296 ,  G06F12/0238 ,  G11C5/147 ,  G11C7/10 ,  G11C7/20 ,  G11C7/22 ,  G11C16/26 ,  G11C16/30 ,  H10B41/30 ,  H10B41/40 ,  G06F1/3275 ,  G11C2207/2227

摘要： A power management circuit that has multiple sets of circuits to provide certain same power management functionalities in different power modes, such as voltage, current and temperature sensing and/or measuring, generating of reference states or biases to effectuate circuit protection in various conditions, such as under voltages, over voltages, etc. One set of circuits is configured to operate during a normal mode and is optimized for performance, speed and/or accuracy. Another set of circuits is configured to operate during a sleep mode and is optimized for reduced power consumption where the performance, speed and/or accuracy may be inferior to the circuits for the normal mode but the functionality is maintained within the low power consumption constraint.

公开(公告)号：US12073916B2

公开(公告)日：2024-08-27

申请号：US18138305

申请日：2023-04-24

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Der Chih

IPC分类号： G06F11/00 ,  G06F1/30 ,  G06F11/14 ,  G06F11/30 ,  G11C5/14 ,  G11C7/20 ,  G11C11/4072

CPC分类号： G11C7/20 ,  G06F1/30 ,  G06F11/1469 ,  G06F11/3037 ,  G06F11/3058 ,  G11C5/148 ,  G11C11/4072

摘要： A system includes: a processor; a register configured to store a plurality of words, non-volatile memory having a plurality of cells, each cell corresponding to one of the words of the register, and wherein the each cell of the plurality of cells are set to an initial reset value; a first controller that in response to a loss in power: determines the word stored by the register; and changes the initial reset value of the cell of the non-volatile memory corresponding to the determined word stored by the register to a set value; a second controller that in response to detecting a restoration in power: identifies the cell having the set value; writes the word corresponding to the identified cell to the register; and resets the cells of the non-volatile memory to the initial reset value.

公开(公告)号：US20240281149A1

公开(公告)日：2024-08-22

申请号：US18645697

申请日：2024-04-25

申请人： Kioxia Corporation

发明人： Junji YANO ,  Hidenori MATSUZAKI ,  Kosuke HATSUDA

IPC分类号： G06F3/06 ,  G06F11/14 ,  G06F12/02 ,  G11C7/20 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10

CPC分类号： G06F3/0619 ,  G06F3/0647 ,  G06F3/065 ,  G06F3/0652 ,  G06F3/0685 ,  G06F11/1456 ,  G06F11/1471 ,  G06F12/0246 ,  G11C7/20 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/105 ,  G06F11/1469 ,  G06F2201/84 ,  G06F2212/7201 ,  G06F2212/7207

摘要： A memory system includes a management-information restoring unit. The management-information restoring unit determines whether a short break has occurred referring to a pre-log or a post-log in a NAND memory. The management-information restoring unit determines that a short break has occurred when the pre-log or the post-log is present in the NAND memory. In that case, the management-information restoring unit determines timing of occurrence of the short break, and, after selecting a pre-log or a post-log used for restoration, performs restoration of the management information reflecting these logs on a snapshot. Thereafter, the management-information restoring unit applies recovery processing to all write-once blocks in the NAND memory, takes the snapshot again, and opens the snapshot and the logs in the past.

公开(公告)号：US20240221804A1

公开(公告)日：2024-07-04

申请号：US18538652

申请日：2023-12-13

申请人： Micron Technology, Inc.

发明人： Yue WANG ,  Jingcheng YUAN

IPC分类号： G11C7/10 ,  G11C7/20 ,  G11C7/22

CPC分类号： G11C7/1096 ,  G11C7/20 ,  G11C7/222

摘要： In some implementations, a memory device may receive a write command indicating data to be programmed. The memory device may determine a programming time, from a first programming time and a second programming time, to be used to program the data, wherein the programming time indicates an amount of time to be associated with programming the data, and wherein the first programming time is associated with a first amount of time and the second programming time is associated with a second amount of time. The memory device may program the data to a memory of the memory device using the programming time.

公开(公告)号：US20240161800A1

公开(公告)日：2024-05-16

申请号：US18056158

申请日：2022-11-16

申请人： NVIDIA Corp.

发明人： Mahmut Ersin Sinangil ,  Sudhir Shrikantha Kudva ,  Nikola Nedovic ,  Carl Thomas Gray

IPC分类号： G11C7/24 ,  G11C7/10 ,  G11C7/20

CPC分类号： G11C7/24 ,  G11C7/1063 ,  G11C7/20

摘要： PUF cells utilizing a dual-interlocking scheme demonstrating improved noise immunity and stability across different V/T conditions and different uses over time in noisy environments. The PUF cell may be advantageously utilized in conjunction with error detection techniques that screen out unstable cells. A set of such PUF cells utilized to generate a device-specific bit pattern, for example a master key.

公开(公告)号：US11935620B2

公开(公告)日：2024-03-19

申请号：US17353592

申请日：2021-06-21

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Yue-Der Chih ,  Cheng-Hsiung Kuo ,  Gu-Huan Li ,  Chien-Yin Liu

IPC分类号： G11C16/04 ,  G11C5/02 ,  G11C7/20 ,  G11C11/16 ,  G11C11/406 ,  G11C13/00

CPC分类号： G11C7/20 ,  G11C5/02 ,  G11C11/1659 ,  G11C11/1677 ,  G11C11/406 ,  G11C13/0033 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0076

摘要： A memory device for memory cell programming and erasing with refreshing operation is disclosed. The memory device includes multiple location-related memory cells and a refresh module. The location-related memory cells are coupled to a bit line on which a selecting voltage is applied. The refresh module rewrites a stored data of a first cell of the location-related memory cells to the first cell of the location-related memory cells in response to an operation count being smaller than a number N. N is related to the number of the location-related memory cells.