公开(公告)号：US5434987A

公开(公告)日：1995-07-18

申请号：US350379

申请日：1994-12-05

申请人： Jeffrey M. Abramson ,  Haitham Akkary ,  Andrew F. Glew ,  Glenn J. Hinton ,  Kris G. Konigsfeld ,  Paul D. Madland

发明人： Jeffrey M. Abramson ,  Haitham Akkary ,  Andrew F. Glew ,  Glenn J. Hinton ,  Kris G. Konigsfeld ,  Paul D. Madland

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3812

摘要： A number of identical matching circuits are integrated into the store address buffer, one matching circuit to each buffer slot, for generating a number of match signals, one for each detected match, using at most the entire source address of an instruction being fetched and the corresponding portions of the store destination addresses of the buffered store instructions. Additionally, a stall signal generator complimentary to the store address buffer is provided for generating a single stall signal for the bus controller, using the match signals, thereby stalling an instruction fetch from a source address that is potentially a store destination of one of the buffered store instructions with minimal performance cost.

摘要翻译： 将多个相同的匹配电路集成到存储地址缓冲器中，每个缓冲器时隙具有一个匹配电路，用于生成多个匹配信号，每个检测到的匹配一个，最多使用正在读取的指令的整个源地址， 缓存存储指令的存储目标地址的对应部分。 此外，提供与存储地址缓冲器相互补充的失速信号发生器，用于使用匹配信号产生用于总线控制器的单个停止信号，从而阻止来自潜在地存储缓冲器之一的存储目的地的源地址的指令获取 存储指令，性能成本最低。