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    Machine check architecture execution environment for non-microcoded processor
    2.
    发明授权
    Machine check architecture execution environment for non-microcoded processor 有权
    非微处理器的机器检查体系结构执行环境

    公开(公告)号：US09141461B2

    公开(公告)日：2015-09-22

    申请号：US13924585

    申请日：2013-06-23

    Applicant: Willam C. Rash ,  Scott D. Hanh ,  Glenn J. Hinton

    Inventor： Willam C. Rash ,  Scott D. Hanh ,  Glenn J. Hinton

    IPC: G06F11/00 ,  G06F11/07 ,  G06F11/14

    CPC classification number: G06F11/0772 ,  G06F11/0724 ,  G06F11/1415 ,  G06F11/142 ,  G06F11/1443 ,  G06F2201/815

    Abstract: A technology for implementing a method for a machine check architecture environment. A method of the disclosure includes obtaining an occurrence of an error. The occurrence of the error causes a non-microcoded processing device to enter an error monitoring state. The method further processes the error using a dedicated memory portion for the error monitoring state while the non-microcoded processing device is in the error monitoring state. The error monitoring state is dedicated to error processing. The method further determines information associated with the error. The information associated with the error is in a predefined format.

    Abstract translation: 一种用于实现机器检查架构环境的方法的技术。 本公开的方法包括获得错误的发生。 错误的发生导致非微编码处理设备进入错误监视状态。 该方法使用专用存储器部分处理错误，用于错误监视状态，而非微编码处理设备处于错误监视状态。 错误监控状态专用于错误处理。 该方法进一步确定与错误相关联的信息。 与错误相关联的信息是预定义的格式。

    DYNAMIC PARTIAL POWER DOWN OF MEMORY-SIDE CACHE IN A 2-LEVEL MEMORY HIERARCHY
    3.
    发明申请
    DYNAMIC PARTIAL POWER DOWN OF MEMORY-SIDE CACHE IN A 2-LEVEL MEMORY HIERARCHY 审中-公开
    内存层高速缓存的动态部分功耗在二级存储器层次上

    公开(公告)号：US20140304475A1

    公开(公告)日：2014-10-09

    申请号：US13994726

    申请日：2011-12-20

    Applicant: Raj K Ramanujan ,  Glenn J Hinton ,  David J Zimmerman

    Inventor： Raj K Ramanujan ,  Glenn J Hinton ,  David J Zimmerman

    IPC: G06F12/08

    Abstract: A system and method are described for flushing a specified region of a memory side cache (MSC) within a multi-level memory hierarchy. For example, a computer system according to one embodiment comprises: a memory subsystem comprised of a non-volatile system memory and a volatile memory side cache (MSC) for caching portions of the non-volatile system memory; and a flush engine for flushing a specified region of the MSC to the non-volatile system memory in response to a deactivation condition associated with the specified region of the MSC.

    Abstract translation: 描述了用于刷新多级存储器层级内的存储器侧缓存（MSC）的指定区域的系统和方法。 例如，根据一个实施例的计算机系统包括：由非易失性系统存储器和用于高速缓存非易失性系统存储器的部分的易失性存储器侧缓存（MSC）组成的存储器子系统; 以及冲洗引擎，用于响应于与MSC的指定区域相关联的去激活条件，将MSC的指定区域冲入非易失性系统存储器。

    INSTRUCTION EMULATION PROCESSORS, METHODS, AND SYSTEMS
    4.
    发明申请
    INSTRUCTION EMULATION PROCESSORS, METHODS, AND SYSTEMS 有权
    指令仿真处理器，方法和系统

    公开(公告)号：US20140281399A1

    公开(公告)日：2014-09-18

    申请号：US13844881

    申请日：2013-03-16

    Applicant: WILLIAM C. RASH ,  BRET L. TOLL ,  SCOTT D. HAHN ,  GLENN J. HINTON

    Inventor： WILLIAM C. RASH ,  BRET L. TOLL ,  SCOTT D. HAHN ,  GLENN J. HINTON

    IPC: G06F9/30

    CPC classification number: G06F9/30145 ,  G06F9/3017 ,  G06F9/30189

    Abstract: A processor of an aspect includes decode logic to receive a first instruction and to determine that the first instruction is to be emulated. The processor also includes emulation mode aware post-decode instruction processor logic coupled with the decode logic. The emulation mode aware post-decode instruction processor logic is to process one or more control signals decoded from an instruction. The instruction is one of a set of one or more instructions used to emulate the first instruction. The one or more control signals are to be processed differently by the emulation mode aware post-decode instruction processor logic when in an emulation mode than when not in the emulation mode. Other apparatus are also disclosed as well as methods and systems.

    Abstract translation: 一方面的处理器包括用于接收第一指令并确定要仿真第一指令的解码逻辑。 处理器还包括与解码逻辑耦合的仿真模式感知后解码指令处理器逻辑。 仿真模式感知后解码指令处理器逻辑是处理从指令解码的一个或多个控制信号。 该指令是用于模拟第一条指令的一组或多条指令之一。 当仿真模式下的仿真模式识别后解码指令处理器逻辑比未处于仿真模式时，一个或多个控制信号被不同地处理。 还公开了其他装置以及方法和系统。

    APPARATUS AND METHOD FOR IMPLEMENTING A MULTI-LEVEL MEMORY HIERARCHY HAVING DIFFERENT OPERATING MODES
    5.
    发明申请
    APPARATUS AND METHOD FOR IMPLEMENTING A MULTI-LEVEL MEMORY HIERARCHY HAVING DIFFERENT OPERATING MODES 有权
    用于实现具有不同操作模式的多级记忆层次的装置和方法

    公开(公告)号：US20130268728A1

    公开(公告)日：2013-10-10

    申请号：US13994731

    申请日：2011-09-30

    Applicant: Raj K. Ramanujan ,  Rajat Agarwal ,  Glenn J. Hinton

    Inventor： Raj K. Ramanujan ,  Rajat Agarwal ,  Glenn J. Hinton

    IPC: G06F12/08

    CPC classification number: G06F12/0811 ,  G06F12/0246 ,  G06F12/0806 ,  G06F12/0808 ,  G06F12/0815 ,  G06F12/0888 ,  G06F12/0893 ,  G06F2212/205 ,  G06F2212/283 ,  G06F2212/6046 ,  G06F2212/621 ,  G06F2212/7201 ,  G11C7/1045 ,  G11C7/1072 ,  G11C13/0004 ,  G11C14/0045

    Abstract: A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.” In one embodiment, the “near memory” is configured to operate in a plurality of different modes of operation including (but not limited to) a first mode in which the near memory operates as a memory cache for the far memory and a second mode in which the near memory is allocated a first address range of a system address space with the far memory being allocated a second address range of the system address space, wherein the first range and second range represent the entire system address space.

    Abstract translation: 描述了用于集成包括计算机系统内的非易失性存储器层的存储器和存储层级的系统和方法。 在一个实施例中，PCMS存储器件被用作层次结构中的一个层，有时被称为“远存储器”。 更高性能的存储器件，例如放置在远存储器之前的DRAM，并用于掩盖远存储器的一些性能限制。 这些更高性能的存储器件被称为“接近存储器”。 在一个实施例中，“近存储器”被配置为以多种不同的操作模式操作，包括（但不限于）其中近端存储器作为远存储器的存储器高速缓存操作的第一模式，以及第二模式 其中所述近存储器被分配有系统地址空间的第一地址范围，所述远存储器被分配了所述系统地址空间的第二地址范围，其中所述第一范围和第二范围表示整个系统地址空间。

    PROCESSOR HAVING EXECUTION CORE SECTIONS OPERATING AT DIFFERENT CLOCK RATES
    7.
    发明申请
    PROCESSOR HAVING EXECUTION CORE SECTIONS OPERATING AT DIFFERENT CLOCK RATES 审中-公开
    具有执行核心部分的处理器以不同的时钟速率运行

    公开(公告)号：US20120042151A1

    公开(公告)日：2012-02-16

    申请号：US12879872

    申请日：2010-09-10

    Applicant: David J. Sager ,  Thomas D. Fletcher ,  Glenn J. Hinton ,  Michael D. Upton

    Inventor： David J. Sager ,  Thomas D. Fletcher ,  Glenn J. Hinton ,  Michael D. Upton

    IPC: G06F15/76 ,  G06F9/02

    CPC classification number: G06F9/3842 ,  G06F1/08 ,  G06F9/30145 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3863 ,  G06F9/3869 ,  G06F15/7832

    Abstract: A processor including a first execution core section clocked to perform execution operations at a first clock frequency, and a second execution core section clocked to perform execution operations at a second clock frequency which is different than the first clock frequency. The second execution core section runs faster and includes a data cache and critical ALU functions, while the first execution core section includes latency-tolerant functions such as instruction fetch and decode units and non-critical ALU functions. The processor may further include an I/O ring which may be still slower than the first execution core section. Optionally, the first execution core section may include a third execution core section whose clock rate is between that of the first and second execution core sections. Clock multipliers/dividers may be used between the various sections to derive their clocks from a single source, such as the I/O clock.

    Abstract translation: 一种处理器，包括以第一时钟频率执行执行操作的第一执行核心部分和第二执行核心部分，其被计时以在与第一时钟频率不同的第二时钟频率执行执行操作。 第二个执行核心部分运行速度更快，包括数据高速缓存和关键的ALU功能，而第一个执行核心部分包括延迟容忍功能，如指令提取和解码单元以及非关键ALU功能。 处理器还可以包括可能仍然比第一执行核心部分慢的I / O环。 可选地，第一执行核心部分可以包括其时钟速率在第一执行核心部分和第二执行核心部分之间的第三执行核心部分。 可以在各部分之间使用时钟乘法器/分频器，以从单个源（例如I / O时钟）导出其时钟。

    Processor having execution core sections operating at different clock rates
    10.
    发明授权
    Processor having execution core sections operating at different clock rates 有权
    具有执行核心部分以不同时钟速率工作的处理器

    公开(公告)号：US06256745B1

    公开(公告)日：2001-07-03

    申请号：US09527065

    申请日：2000-03-16

    Applicant: David J. Sager ,  Thomas D. Fletcher ,  Glenn J. Hinton ,  Michael D. Upton

    Inventor： David J. Sager ,  Thomas D. Fletcher ,  Glenn J. Hinton ,  Michael D. Upton

    IPC: G06F106

    CPC classification number: G06F1/02 ,  G06F1/06 ,  G06F1/08 ,  G06F9/30145 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3863 ,  G06F9/3869 ,  G06F15/7832

    Abstract: A processor including a first execution core section clocked to perform execution operations at a first clock frequency, and a second execution core section clocked to perform execution operations at a second clock frequency which is different than the first clock frequency. The second execution core section runs faster and includes a data cache and critical ALU functions, while the first execution core section includes latency-tolerant functions such as instruction fetch and decode units and non-critical ALU functions. The processor may further include an I/O ring which may be still slower than the first execution core section optionally, the first execution core section may include a third execution core section whose clock rate is between that of the first and second execution core sections. Clock multipliers/dividers may be used between the various sections to derive their clocks from a single source, such as the I/O clock.

    Abstract translation: 一种处理器，包括以第一时钟频率执行执行操作的第一执行核心部分和第二执行核心部分，其被计时以在与第一时钟频率不同的第二时钟频率执行执行操作。 第二个执行核心部分运行速度更快，包括数据高速缓存和关键的ALU功能，而第一个执行核心部分包括延迟容忍功能，如指令提取和解码单元以及非关键ALU功能。 处理器还可以包括可能比第一执行核心部分慢的I / O环，可选地，第一执行核心部分可以包括其时钟速率在第一和第二执行核心部分之间的时钟速率的第三执行核心部分。 可以在各部分之间使用时钟乘法器/分频器，以从单个源（例如I / O时钟）导出其时钟。

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