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公开(公告)号：US07010073B2
公开(公告)日：2006-03-07
申请号：US10044235
申请日：2002-01-11
IPC分类号： H04L7/00
摘要： Techniques for deriving sample timing for multiple signal instances received on multiple antennas for a given propagation path. In one scheme, a DLL is maintained for each path, and each DLL tracks the timing of the best signal instance for the assigned path. In another scheme, a DLL is maintained for each path, and each DLL tracks the average timing of the multiple signal instances for the assigned path. To reduce timing jitter, the SINR of a signal instance may be estimated for a number of different time offsets. The loop filter for the DLL is initially updated in the normal manner. If a change in the time offset used for the sample timing is detected, then the SINRs for the new and prior offsets are compared. The new time offset is used if the associated SINR is better. Otherwise, the prior time offset is retained and used.
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公开(公告)号：US06738608B2
公开(公告)日：2004-05-18
申请号：US10075578
申请日：2002-02-12
IPC分类号： H04B106
CPC分类号： H04L7/0054 , H04B2001/70706 , H04L7/0025 , H04L27/0014 , H04L2027/0028 , H04L2027/0036 , H04L2027/0055 , H04L2027/0065
摘要： A frequency-timing control loop comprising (1) a frequency control loop to acquire and track the frequency of a given signal instance in a received signal and (2) a timing control loop to acquire and track the timing of the same signal instance. The timing control loop processes data samples for the received signal to provide a first control indicative of timing error in the data samples for the signal instance. The frequency control loop includes (1) a frequency discriminator used to derive a second control indicative of frequency error in the data samples for the signal instance, and (2) a loop filter used to filter the first and second controls to provide a third control. This third control is used to adjust the frequency and phase of a periodic signal, which is used (directly or indirectly) to downconvert and digitize the received signal to provide the data samples.
摘要翻译： 一种频率定时控制环路，包括：（1）频率控制环路，用于获取并跟踪接收信号中的给定信号实例的频率，以及（2）定时控制环路，用于获取和跟踪同一信号实例的定时。 定时控制环路处理接收信号的数据样本，以提供指示信号实例的数据采样中的定时误差的第一控制。 频率控制回路包括（1）用于导出指示信号实例的数据样本中的频率误差的第二控制的频率鉴别器，以及（2）用于对第一和第二控制进行滤波以提供第三控制的环路滤波器 。 该第三控制用于调整周期性信号的频率和相位（直接或间接使用）来对接收信号进行下变频和数字化，以提供数据样本。
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63.发明授权Method and apparatus for generating multiple bits of a pseudonoise sequence with each clock pulse by computing the bits in parallel 有权用于通过并行计算比特来产生具有每个时钟脉冲的伪噪声序列的多个比特的方法和装置公开(公告)号：US06640236B1
公开(公告)日：2003-10-28
申请号：US09386600
申请日：1999-08-31
IPC分类号： G06F102
CPC分类号： G06F7/584
摘要： The invention presented is a novel method and apparatus for generating PN sequences with an arbitrary number of bits, where the number of bits is provided in parallel with each clock pulse. This allows the sequences to be generated at high speed when needed, and allows parallel processing in the acquisition and demodulation processes. In the invention, the initial values of states are loaded into registers of a parallel PN generator, which immediately generates the next n bits of the PN sequence, where n is an arbitrary number dependent on performance required. Then, a first sub-part of the PN generator of the present invention receives the present state of the PN generator and outputs the state of the PN generator n bits in the future. The output of this first sub-part is then provided to a second sub-part of the generator, which generates the next n bits of the PN sequence. In this fashion, the entire PN sequence can be continuously generated. The PN generator also contains a control processor, coordinating co-operation between sub-systems.
摘要翻译： 所提出的本发明是用于产生具有任意位数的PN序列的新颖方法和装置，其中与每个时钟脉冲并联提供比特数。 这允许在需要时以高速生成序列，并且允许在采集和解调过程中的并行处理。 在本发明中，将状态的初始值加载到并行PN发生器的寄存器中，其立即生成PN序列的下一个n位，其中n是取决于所需性能的任意数目。 然后，本发明的PN发生器的第一子部分接收PN发生器的当前状态，并在将来输出PN发生器n位的状态。 然后将该第一子部分的输出提供给发生器的第二子部分，其产生PN序列的下一个n位。 以这种方式，可以连续地产生整个PN序列。 PN发生器还包含一个控制处理器，协调子系统之间的协作。
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