公开(公告)号：US12081749B2

公开(公告)日：2024-09-03

申请号：US18142166

申请日：2023-05-02

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Chong Soon Lim ,  Hai Wei Sun ,  Han Boon Teo ,  Jing Ya Li ,  Che-Wei Kuo ,  Kiyofumi Abe ,  Tadamasa Toma ,  Takahiro Nishi ,  Yusuke Kato

IPC: H04N19/117 ,  H04N19/176 ,  H04N19/51 ,  H04N19/80

CPC classification number: H04N19/117 ,  H04N19/176 ,  H04N19/51 ,  H04N19/80

Abstract: An encoder that encodes a current block to be encoded in an image is provided. The encoder includes: processor; and memory coupled to the processor, in which, in operation, the processor: generates a first prediction image based on a motion vector, the first prediction image being an image with full-pel precision; generates a second prediction image using an interpolation filter by interpolating a value at a fractional-pel position between full-pel positions included in the first prediction image; and encodes the current block based on the second prediction image, and in the using of the interpolation filter, the interpolation filter is switched between a first interpolation filter and a second interpolation filter differing in a total number of taps from the first interpolation filter.

公开(公告)号：US12052442B2

公开(公告)日：2024-07-30

申请号：US18133070

申请日：2023-04-11

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Virginie Drugeon ,  Tadamasa Toma ,  Takahiro Nishi ,  Kiyofumi Abe ,  Yusuke Kato

IPC: H04N19/70 ,  H04N19/169 ,  H04N19/423 ,  H04N19/46

CPC classification number: H04N19/70 ,  H04N19/188 ,  H04N19/423 ,  H04N19/46

Abstract: An encoder includes circuitry and memory coupled to the circuitry. In operation, the circuitry: writes, into a sequence parameter set which is header information of a sequence, video usability information syntax which is information for realizing an additional function in display of an image, and syntax different from the video usability information syntax. The syntax includes at least one parameter related to display timing of the image.

公开(公告)号：US12028519B2

公开(公告)日：2024-07-02

申请号：US18071370

申请日：2022-11-29

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Jing Ya Li ,  Chong Soon Lim ,  Hai Wei Sun ,  Han Boon Teo ,  Che Wei Kuo ,  Chu Tong Wang ,  Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma ,  Yusuke Kato

IPC: H04N19/82 ,  H04N19/105 ,  H04N19/117 ,  H04N19/119 ,  H04N19/124 ,  H04N19/13 ,  H04N19/18 ,  H04N19/186

CPC classification number: H04N19/117 ,  H04N19/105 ,  H04N19/119 ,  H04N19/124 ,  H04N19/13 ,  H04N19/18 ,  H04N19/186 ,  H04N19/82

Abstract: An encoder includes circuitry and memory. The circuitry, in operation, generates a first coefficient value by applying a CCALF (cross component adaptive loop filtering) process to a first reconstructed image sample of a luma component. The circuitry generates a second coefficient value by applying an ALF (adaptive loop filtering) process to a second reconstructed image sample of a chroma component. The circuitry generates a third coefficient value by adding the first coefficient value to the second coefficient value, and encodes a third reconstructed image sample of the chroma component using the third coefficient value. In the CCALF process, in response to a coordinate of the second reconstructed image sample being (x, y), coordinates of the first reconstructed image samples are (2x, 2y−1), (2x−1, 2y), (2x, 2y), (2x+1, 2y), (2x−1, 2y+1), (2x, 2y+1), (2x+1, 2y+1), and (2x, 2y+2).

公开(公告)号：US12028513B2

公开(公告)日：2024-07-02

申请号：US17463889

申请日：2021-09-01

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Jing Ya Li ,  Chong Soon Lim ,  Han Boon Teo ,  Hai Wei Sun ,  Che Wei Kuo ,  Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma ,  Yusuke Kato

IPC: H04N19/105 ,  H04N19/159 ,  H04N19/176 ,  H04N19/52

CPC classification number: H04N19/105 ,  H04N19/159 ,  H04N19/176 ,  H04N19/52

Abstract: Provided is an encoder includes: circuitry; and memory coupled to the circuitry, in which in operation, the circuitry: generates a prediction image of a current block to be processed, using a first motion vector; and updates a history based motion vector predictor (HMVP) table using a first candidate having the first motion vector, the HMVP table storing, in a first in first out (FIFO) method, a plurality of second candidates each having a second motion vector used for a processed block, and in the updating of the HMVP table, the circuitry: determines whether a size of the current block is less than or equal to a threshold size; and skips the updating of the HMVP table when the size of the current block is determined to be less than or equal to the threshold size.

公开(公告)号：US12022072B2

公开(公告)日：2024-06-25

申请号：US17992833

申请日：2022-11-22

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Hai Wei Sun ,  Chong Soon Lim ,  Jing Ya Li ,  Han Boon Teo ,  Che-Wei Kuo ,  Chu Tong Wang ,  Tadamasa Toma ,  Takahiro Nishi ,  Kiyofumi Abe ,  Yusuke Kato

IPC: H04N19/117 ,  H04N19/132 ,  H04N19/186 ,  H04N19/82

CPC classification number: H04N19/117 ,  H04N19/132 ,  H04N19/186 ,  H04N19/82

Abstract: An encoder includes circuitry and memory coupled to the circuitry. The circuitry, in operation, generates a first coefficient value by applying a CCALF (cross component adaptive loop filtering) process to a first reconstructed image sample of a luma component, generates a second coefficient value by applying an ALF (adaptive loop filtering) process to a second reconstructed image sample of a chroma component, and clips the second coefficient value. The circuitry generates a third coefficient value by adding the first coefficient value to the clipped second coefficient value, and clips the third coefficient value. The circuitry encodes a third reconstructed image sample of the chroma component using the clipped third coefficient value.

公开(公告)号：US20240114129A1

公开(公告)日：2024-04-04

申请号：US18529380

申请日：2023-12-05

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Jing Ya LI ,  Chong Soon Lim ,  Han Boon Teo ,  Che Wei Kuo ,  Hai Wei Sun ,  Chu Tong Wang ,  Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma ,  Yusuke Kato

IPC: H04N19/105 ,  H04N19/14 ,  H04N19/159 ,  H04N19/176

CPC classification number: H04N19/105 ,  H04N19/14 ,  H04N19/159 ,  H04N19/176

Abstract: An encoder includes circuitry and memory coupled to the circuitry. The circuitry, in operation: determines whether a size of a current block, which is a unit for which a vector candidate list including vector candidates is generated, is less than or equal to a threshold; when the size of the current block is less than or equal to the threshold, generates the vector candidate list by registering a history-based motion vector predictor (HMVP) vector candidate in the vector candidate list from an HMVP table without performing a first pruning process; when the size of the current block is greater than the threshold, generates the vector candidate list by performing the first pruning process and registering the HMVP vector candidate in the vector candidate list from the HMVP table; and encodes the current block using the vector candidate list.

公开(公告)号：US11843799B2

公开(公告)日：2023-12-12

申请号：US17388478

申请日：2021-07-29

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Tadamasa Toma ,  Takahiro Nishi ,  Kiyofumi Abe ,  Yusuke Kato

IPC: H04N19/513 ,  H04N19/86

CPC classification number: H04N19/521 ,  H04N19/86

Abstract: An encoder includes circuitry and memory coupled to the circuitry. In operation, the circuitry: derives a motion vector of a current block by referring to at least one reference picture different from a picture to which the current block belongs; performs a mode for estimating, for each sub-block unit of sub-blocks obtained by splitting the current block, a surrounding region of the motion vector to correct the motion vector; determines whether to apply deblocking filtering to each of boundaries between neighboring ones of the sub-blocks; and applies the deblocking filtering to the boundary, based on a result of the determination.

公开(公告)号：US11825127B2

公开(公告)日：2023-11-21

申请号：US17863123

申请日：2022-07-12

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Chong Soon Lim ,  Hai Wei Sun ,  Han Boon Teo ,  Jing Ya Li ,  Che-Wei Kuo ,  Tadamasa Toma ,  Takahiro Nishi ,  Kiyofumi Abe ,  Yusuke Kato

IPC: H04N19/82 ,  H04N19/119 ,  H04N19/176 ,  H04N19/593

CPC classification number: H04N19/82 ,  H04N19/119 ,  H04N19/176 ,  H04N19/593

Abstract: An encoder includes circuitry and memory coupled to the circuitry. The circuitry determines whether to split a current luma virtual pipeline decoding unit (VPDU) into smaller blocks. When it is determined not to split the current luma VPDU into smaller blocks, the circuitry predicts a block of chroma samples without using luma samples. When it is determined to split the luma VPDU into smaller blocks, the circuitry predicts the block of chroma samples using luma samples. The circuitry encodes the block using the predicted chroma samples.

公开(公告)号：US11770561B2

公开(公告)日：2023-09-26

申请号：US17971817

申请日：2022-10-24

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Masato Ohkawa ,  Hideo Saitou ,  Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma ,  Yusuke Kato

IPC: H04N19/112 ,  H04N19/12 ,  H04N19/16 ,  H04N19/186 ,  H04N19/60 ,  H04N19/119 ,  H04N19/17 ,  H04N19/184 ,  H04N19/30

CPC classification number: H04N19/649 ,  H04N19/112 ,  H04N19/119 ,  H04N19/12 ,  H04N19/16 ,  H04N19/17 ,  H04N19/184 ,  H04N19/186 ,  H04N19/30

Abstract: Provided is an encoder including: circuitry; and memory coupled to the circuitry. In operation, the circuitry: performs a mapping process of Luma Mapping with Chroma Scaling (LMCS) for transforming a first pixel value space applied to a luma display image signal into a second pixel value space applied to a luma encoding process signal, using line segments forming a transform curve, each of which corresponds to a different one of sections obtained by partitioning the first pixel value space; and encodes an image, and in the performing of the LMCS, the circuitry determines the transform curve so that among boundary values in the second pixel value space, a first value obtained by dividing a boundary value by a base width defined according to a bit depth of the image is not equal to a second value obtained by dividing another boundary value by the base width.

公开(公告)号：US11611758B2

公开(公告)日：2023-03-21

申请号：US16795408

申请日：2020-02-19

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Jing Ya Li ,  Chong Soon Lim ,  Han Boon Teo ,  Hai Wei Sun ,  Che Wei Kuo ,  Kiyofumi Abe ,  Takahiro NIshi ,  Tadamasa Toma ,  Yusuke Kato

IPC: G06V30/00 ,  H04N19/159 ,  H04N19/126 ,  H04N19/156 ,  H04N19/18 ,  H04N19/52 ,  H04N19/61

Abstract: An image encoder is provided including circuitry and a memory coupled to the circuitry. The circuitry, in operation, responds to a size of a block satisfying a size condition by generating a prediction image using a prediction mode selected from a plurality of prediction modes. The plurality of prediction modes include a first prediction mode in which a prediction process uses a motion vector and a reference block in a same picture as the block. The circuitry encodes the block using the prediction image.