公开(公告)号：US20140269112A1

公开(公告)日：2014-09-18

申请号：US13863989

申请日：2013-04-16

Applicant: QUALCOMM Incorporated

Inventor： Chulmin Jung ,  Changho Jung ,  Sei Seung Yoon ,  Rakesh Vattikonda ,  Nishith Desai

IPC: G11C7/12

CPC classification number: G11C7/12 ,  G11C7/1084 ,  G11C7/1096 ,  G11C11/419

Abstract: A write driver for a memory circuit includes a control circuit configured to: operate a first push-pull driver to generate a first drive signal in a first voltage domain at a first node based on an input signal in a second domain and in response to a mode select signal being in a first mode, wherein the first drive signal is at a same logic level as the input signal; operate a second push-pull driver to generate a second drive signal in the first voltage domain at a second node based on the input signal and in response to the mode select signal being in the first mode, wherein the second drive signal is at a complement logic level with respect to the input signal; and operate the first and second push-pull drivers to float the first and second nodes in response to the mode select signal being in a second mode.

Abstract translation: 用于存储器电路的写驱动器包括控制电路，该控制电路被配置为：基于第二域中的输入信号，并响应于第一推挽驱动器响应于第一推挽驱动器，在第一节点处的第一电压域中产生第一驱动信号 模式选择信号处于第一模式，其中第一驱动信号处于与输入信号相同的逻辑电平; 操作第二推挽驱动器以基于输入信号在第二节点处的第一电压域中产生第二驱动信号，并且响应于模式选择信号处于第一模式，其中第二驱动信号为补码 相对于输入信号的逻辑电平; 并且响应于所述模式选择信号处于第二模式，操作所述第一和第二推挽驱动器使所述第一和第二节点浮动。