公开(公告)号：US20240347084A1

公开(公告)日：2024-10-17

申请号：US18755033

申请日：2024-06-26

Applicant: Micron Technology, Inc.

Inventor： Robert W. Mason ,  Pitamber Shukla ,  Steven Michael Kientz

IPC: G11C7/10 ,  G11C7/22

CPC classification number: G11C7/1096 ,  G11C7/1069 ,  G11C7/109 ,  G11C7/222

Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including initializing the memory device; selecting at least one sample management unit on the memory device; performing a calibration operation on the sample management unit to determine a duration value reflecting a duration during which the memory device was powered down; adjusting an accumulator value based on the duration value; determining a read voltage value based on the accumulator value; and performing a read operation using the read voltage value.

公开(公告)号：US12112819B2

公开(公告)日：2024-10-08

申请号：US18376198

申请日：2023-10-03

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Sheyang Ning ,  Lawrence Celso Miranda ,  Tomoko Ogura Iwasaki ,  Ting Luo ,  Luyen Vu

IPC: G11C29/42 ,  G11C7/10 ,  G11C29/12 ,  G11C29/44

CPC classification number: G11C29/42 ,  G11C7/1069 ,  G11C7/1096 ,  G11C29/12005 ,  G11C29/4401

Abstract: Apparatus might include an array of memory cells and a controller for access of the array of memory cells. The controller might be configured to cause the apparatus to apply a sense voltage level to a control gate of a memory cell of the array of memory cells, generate N determinations whether the memory cell is deemed to activate or deactivate while applying the sense voltage level, wherein N is an integer value greater than or equal to three, deem the memory cell to have a threshold voltage in a first range of threshold voltages lower than the sense voltage level in response to a majority of the N determinations indicating activation of the memory cell, and deem the memory cell to have a threshold voltage in a second range of threshold voltages higher than the sense voltage level in response to a majority of the N determinations indicating activation of the memory cell.

公开(公告)号：US12106801B2

公开(公告)日：2024-10-01

申请号：US17858376

申请日：2022-07-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jhon Jhy Liaw

IPC: G11C11/412 ,  G11C11/419 ,  G11C5/02 ,  G11C7/10 ,  G11C7/12

CPC classification number: G11C11/419 ,  G11C11/412 ,  G11C5/025 ,  G11C7/1096 ,  G11C7/12

Abstract: An array of memory cells is arranged into a plurality of columns and rows. A first signal line extends through a first column of the plurality of columns. The first signal line is electrically coupled to the memory cells in the first column. A first end portion of the first signal line is configured to receive a logic high signal from a first circuit during a first operational state of the memory device and a logic low signal from the first circuit during a second operational state of the memory device. A second circuit includes a plurality of transistors. The transistors are configured to be turned on or off to electrically couple a second end portion of the first signal line to a logic low source when the first end portion of the first signal line is configured to receive the logic low signal from the first circuit.

公开(公告)号：US20240321382A1

公开(公告)日：2024-09-26

申请号：US18589628

申请日：2024-02-28

Applicant: Kioxia Corporation

Inventor： Junji YAMADA

IPC: G11C29/52 ,  G11C7/10

CPC classification number: G11C29/52 ,  G11C7/1069 ,  G11C7/1096

Abstract: A semiconductor memory device includes a memory cell array configured to store data, and a control circuit configured to control a write operation of writing data into the memory cell array. In the write operation, the control circuit is configured to receive first data and second data including a parity bit, generate a parity bit for the first data, check whether the parity bit and the parity bit match with each other, and write the first data into the memory cell array.

公开(公告)号：US12092513B2

公开(公告)日：2024-09-17

申请号：US17298929

申请日：2019-12-03

Applicant: SONELITE INC.

Inventor： Paul Graeme Bremner ,  Christopher Todter

IPC: G01H3/12 ,  H04R1/40 ,  H04R3/00 ,  H04R19/04 ,  G11C7/10

CPC classification number: G01H3/125 ,  H04R1/406 ,  H04R3/005 ,  H04R19/04 ,  G11C7/1096 ,  H04R2201/003 ,  H04R2201/401

Abstract: Sensor devices, systems, and methods for measuring different components of a flow are provided. A sensing arrangement includes a substrate and first and second sensor arrays on the substrate. The first sensor array sensing elements are distributed to obtain measurement data indicative of a first property of an operating environment, such as a turbulent component of a fluid flow. The second sensor array sensing elements are interspersed amongst the first sensor array and distributed to obtain measurement data indicative of a second property of the operating environment, such as an acoustic component of the fluid flow.

公开(公告)号：US12080379B2

公开(公告)日：2024-09-03

申请号：US17939016

申请日：2022-09-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Baek Jin Lim ,  Youngchul Cho ,  Seungjin Park ,  Doobock Lee ,  Youngdon Choi ,  Junghwan Choi

IPC: G11C7/22 ,  G11C7/06 ,  G11C7/10

CPC classification number: G11C7/222 ,  G11C7/06 ,  G11C7/1096

Abstract: A semiconductor device according to an embodiment includes a plurality of sampler circuits configured to receive a plurality of offset clock signals or a plurality of divided clock signals and to sample a data signal in response to each of a plurality of divided clock signals. A calibration circuit applies a first offset clock signal to a first sampler circuit, applies a second offset clock signal having an opposite phase to the first offset clock signal to a second sampler circuit, and generates a first offset adjustment signal for adjusting an offset of the first sampler circuit based on an output of the first sampler circuit that is output in response to the first offset clock signal.

公开(公告)号：US12080377B2

公开(公告)日：2024-09-03

申请号：US17802281

申请日：2021-03-04

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuki Okamoto ,  Tatsuya Onuki ,  Munehiro Kozuma ,  Takanori Matsuzaki

IPC: G11C7/10 ,  G11C7/12 ,  G11C8/08 ,  H01L29/786 ,  H10B12/00

CPC classification number: G11C7/1096 ,  G11C7/12 ,  G11C8/08 ,  H01L29/7869 ,  H10B12/31 ,  H10B12/50

Abstract: A semiconductor device with a novel structure is provided. The semiconductor device includes a plurality of arithmetic blocks each including an arithmetic circuit portion and a memory circuit portion. The arithmetic circuit portion and the memory circuit portion are electrically connected to each other. The arithmetic circuit portion and the memory circuit portion have an overlap region. The arithmetic circuit portion includes, for example, a Si transistor, and the memory circuit portion includes, for example, an OS transistor. The arithmetic circuit portion has a function of performing product-sum operation. The memory circuit portion has a function of retaining weight data. A first driver circuit has a function of writing the weight data to the memory circuit portion. The weight data is written to all the memory circuit portions included in the same column with the use of the first driver circuit.

公开(公告)号：US12068055B2

公开(公告)日：2024-08-20

申请号：US17899417

申请日：2022-08-30

Applicant: Micron Technology, Inc.

Inventor： Abhilash Ramamurthy Nag ,  Suresh Reddy Yarragunta ,  Shiva Pahwa

IPC: G11C7/10 ,  G06F11/30 ,  G06N20/00 ,  G11C29/00 ,  G11C29/52

CPC classification number: G11C7/1096 ,  G06F11/3058 ,  G06N20/00 ,  G11C7/1093 ,  G11C29/00 ,  G11C29/52 ,  G11C2207/2245 ,  G11C2207/229

Abstract: Exemplary methods, apparatuses, and systems include an environmental operations manager for controlling memory access of the memory device. The environmental operations manager receives a set of data bits for programming to a memory location. The environmental operations manager receives environmental condition data. The environmental operations manager delays programming of the set of data bits to the memory location and writing the set of data bits to a buffer location in response to determining that the environmental condition data satisfies a threshold.

公开(公告)号：US20240265955A1

公开(公告)日：2024-08-08

申请号：US18164570

申请日：2023-02-04

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Shun-Ke Wu

IPC: G11C7/22 ,  G11C7/10

CPC classification number: G11C7/222 ,  G11C7/1093 ,  G11C7/1096

Abstract: An electronic device, a memory device of the electronic device, and a write leveling method of the memory device are provided. The memory device is coupled to a memory controller to receive a data strobe signal DQS and a clock signal CLK. In a write leveling mode, the memory device provides a write leveling function to the memory controller, where the write leveling function includes a plurality of iterative operations. In each of the iterative operations, the memory controller sends a notification to the memory device, and the memory device sets up a strobe window based on the notification. The memory device samples the clock signal CLK based on a phase of the data strobe signal DQS in the strobe window, so as to send a sampling result back to the memory controller. The memory device is prohibited from sampling the clock signal CLK outside the strobe window.

公开(公告)号：US12057190B2

公开(公告)日：2024-08-06

申请号：US17897438

申请日：2022-08-29

Applicant: Micron Technology, Inc.

Inventor： Robert W. Mason ,  Pitamber Shukla ,  Steven Michael Kientz

IPC: G11C16/10 ,  G11C7/10 ,  G11C7/22

CPC classification number: G11C7/1096 ,  G11C7/1069 ,  G11C7/109 ,  G11C7/222

Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including periodically, at a predefined frequency, incrementing a value stored in an accumulator by a composite parameter value; responsive to receiving a program request specifying a data item to be programmed to a management unit of the memory device, obtaining a first value from the accumulator; storing the first value to a program reference table; programming the data item to the management unit; responsive to receiving a read request specifying the management unit, obtaining a second value from the accumulator; determining a read voltage value based on a difference of the first value and the second value; and performing a read operation, using the read voltage value, on the management unit.