Data communications device and associated method for arbitrating access using dynamically programmable arbitration scheme and limits on data transfers
    61.
    发明授权
    Data communications device and associated method for arbitrating access using dynamically programmable arbitration scheme and limits on data transfers 有权
    数据通信设备和相关方法用于使用动态可编程仲裁方案仲裁访问和数据传输限制

    公开(公告)号:US06345345B1

    公开(公告)日:2002-02-05

    申请号:US09236586

    申请日:1999-01-26

    Applicant: Ching Yu Jerry Kuo

    Inventor: Ching Yu Jerry Kuo

    CPC classification number: G06F13/1605

    Abstract: Data communications device and method for arbitrating access to a system memory of the communications device via a peripheral component interconnect (PCI) bus in a network interface having a memory management unit for managing transmit data transfers from the system memory to a transmit buffer memory, and receive data transfers from a receive buffer memory to the system memory. The memory management unit includes an arbitration block having an arbiter state machine, which receives requests for access to the PCI bus in order to provide the transmission and reception of data, descriptors and status information. The arbiter state machine grants the PCI bus access to a request having a higher priority in accordance with a preset priority scheme. The memory management unit has a transmit transfer control register and a receive transfer control register containing programmable values that limit the maximum number of transmit data transfers and receive data transfers allowed within a single PCI bus mastership period. Also, the transmit and receive transfer control registers contain programmable values that limit the number of allowed transmit data transfers within a single PCI bus mastership period when a request for a receive data transfer is asserted, and limit the number of allowed receive data transfers in a PCI bus mastership period when a request for a transmit data transfer is active. The transfer control values in the transmit and receive transfer control registers are dynamically programmed by a host based on data traffic in the PCI bus. Also, the transmit and receive transfer control register values may be preprogrammed based on the network interface application, for example, whether the network interface is used in a network client or network file server.

    Abstract translation: 一种数据通信装置和方法,用于通过具有用于管理从系统存储器向发送缓冲存储器的发送数据传送的存储器管理单元的网络接口中经由外围组件互连(PCI)总线仲裁对通信设备的系统存储器的访问的数据通信设备和方法,以及 接收从接收缓冲存储器到系统存储器的数据传输。 存储器管理单元包括具有仲裁器状态机的仲裁块,其接收对PCI总线的访问请求,以便提供数据,描述符和状态信息的发送和接收。 仲裁器状态机根据预设的优先级方案授予PCI总线访问具有较高优先级的请求。 存储器管理单元具有发送传输控制寄存器和接收传送控制寄存器,其包含可限制发送数据传输的最大数量并接收在单个PCI总线主管期内允许的数据传输的可编程值。 此外,发送和接收传输控制寄存器包含可编程值,当有效的接收数据传输请求被断言时,限制在单个PCI总线主管期内允许的发送数据传输的数量,并且限制在 当传输数据传输请求处于活动状态时,PCI总线主管期限。 发送和接收传输控制寄存器中的传输控制值由主机根据PCI总线中的数据流量进行动态编程。 此外,发送和接收转移控制寄存器值可以基于网络接口应用程序进行预编程,例如,网络接口是否用于网络客户端或网络文件服务器。

    Using an index and count mechanism to coordinate access to a shared
resource by interactive devices
    62.
    发明授权
    Using an index and count mechanism to coordinate access to a shared resource by interactive devices 失效
    使用索引和计数机制来协调交互式设备对共享资源的访问

    公开(公告)号:US6070194A

    公开(公告)日:2000-05-30

    申请号:US992148

    申请日:1997-12-17

    CPC classification number: G06F15/167

    Abstract: Th present invention coordinates access to a shared resource, comprised of a plurality of segments, between a first device and a second device using an index and count mechanism. The present invention includes a respective descriptor, for each of the plurality of segments. Entries to the respective descriptors of the segments are maintained by the first device to inform the second device of activity between the first device and the shared resource. The present invention also includes a descriptor queue register, coupled to the first device and the second device. The first device writes an index into the descriptor queue register for indicating a starting descriptor of a corresponding segment that is available to the second device for access. The first device also writes a count into the descriptor queue register for indicating a subsequent number of descriptors, from the starting descriptor, of any corresponding segments that are available to the second device for access. By thus using this index and count mechanism, the second device does not poll the descriptors to determine any available segments within the shared resource thereby substantially eliminating bandwidth, delay, and data processing overhead associated with the polling process of the prior art. The present invention can be used to particular advantage when the first device is a CPU of a computer host system having a shared memory which is the shared resource and when the second device is a computer network peripheral device that couples the computer host system to a network of computers.

    Abstract translation: 本发明使用索引和计数机制来协调对第一设备和第二设备之间的由多个段组成的共享资源的访问。 对于多个段中的每一个,本发明包括相应的描述符。 分段的相应描述符的条目由第一设备维护以通知第二设备第一设备和共享资源之间的活动。 本发明还包括耦合到第一设备和第二设备的描述符队列寄存器。 第一个设备将一个索引写入描述符队列寄存器,用于指示可用于第二个设备进行访问的相应段的起始描述符。 第一个设备还将一个计数写入描述符队列寄存器,用于指示来自起始描述符的随后数量的可用于第二设备访问的任何相应段的描述符。 通过这样使用该索引和计数机制,第二设备不轮询描述符来确定共享资源内的任何可用段,从而基本上消除了与现有技术的轮询过程相关联的带宽,延迟和数据处理开销。 当第一设备是具有作为共享资源的共享存储器的计算机主机系统的CPU以及当第二设备是将计算机主机系统耦合到网络的计算机网络外围设备时,本发明可以被用于特别的优点 的电脑。

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