公开(公告)号：US20120084066A1

公开(公告)日：2012-04-05

申请号：US12894286

申请日：2010-09-30

申请人： Nathan C. Buck ,  Brian M. Dreibelbis ,  John P. Dubuque ,  Eric A. Foreman ,  Peter A. Habitz ,  Jeffrey G. Hemmett ,  Natesan Venkateswaran ,  Chandramouli Visweswariah ,  Xiaoyue X. Wang

发明人： Nathan C. Buck ,  Brian M. Dreibelbis ,  John P. Dubuque ,  Eric A. Foreman ,  Peter A. Habitz ,  Jeffrey G. Hemmett ,  Natesan Venkateswaran ,  Chandramouli Visweswariah ,  Xiaoyue X. Wang

IPC分类号： G06F17/50

CPC分类号： G06F13/105 ,  G06F11/261 ,  G06F17/50 ,  G06F17/5036

摘要： A computer-implemented method that simulates NPskew effects on a combination NFET (Negative Field Effect Transistor)/PFET (Positive Field Effect Transistor) semiconductor device using slew perturbations includes performing a timing test by a computing device, by: (1) evaluating perturb slews in Strong N/Weak P directions on the combination semiconductor device for a timing test result; (2) evaluation perturb slews in Weak N/Strong P directions on the combination semiconductor device for a timing test result; and (3) evaluating unperturbed slews in a balanced condition on the combination semiconductor device for a timing test result. After each test is performed, a determination is made as to which evaluation of the perturbed and unperturbed slews produces a most conservative timing test result for the combination semiconductor device. An NPskew effect adjusted timing test result is finally output based on determining the most conservative timing test result.

摘要翻译： 使用摆动扰动模拟组合NFET（负场效应晶体管）/ PFET（正场效应晶体管）/ PFET（正场效应晶体管））半导体器件的NPskew效应的计算机实现的方法包括通过以下方式执行计算设备的定时测试：（1）评估干扰压摆 在组合半导体器件上以强N /弱P方向进行定时测试结果; （2）组合半导体器件的评估扰动在弱N /强P方向上的时序测试结果; 和（3）在组合半导体器件上对平衡状态下的非扰动压摆进行定时测试结果。 在执行每个测试之后，确定扰动和未扰动的压摆的哪个评估对组合半导体器件产生最保守的定时测试结果。 基于确定最保守的定时测试结果，最终输出NPskew效果调整的定时测试结果。

公开(公告)号：US08141012B2

公开(公告)日：2012-03-20

申请号：US12549061

申请日：2009-08-27

申请人： Nathan C. Buck ,  Brian M. Dreibelbis ,  John P. Dubuque ,  Eric A. Foreman ,  Peter A. Habitz ,  Jeffrey G. Hemmett ,  Susan K. Lichtensteiger ,  Natesan Venkateswaran ,  Chandramouli Visweswariah ,  Xiaoyue Wang

发明人： Nathan C. Buck ,  Brian M. Dreibelbis ,  John P. Dubuque ,  Eric A. Foreman ,  Peter A. Habitz ,  Jeffrey G. Hemmett ,  Susan K. Lichtensteiger ,  Natesan Venkateswaran ,  Chandramouli Visweswariah ,  Xiaoyue Wang

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F2217/84

摘要： An approach for covering multiple selective timing corners in a single statistical timing run is described. In one embodiment, a single statistical timing analysis is run on the full parameter space that covers unlimited process parameters/environment conditions. Results from the statistical timing analysis are projected for selected corners. Timing closure is performed on the corners having the worst slacks.

摘要翻译： 描述了在单个统计时序运行中覆盖多个选择性定时角的方法。 在一个实施例中，在涵盖无限制过程参数/环境条件的完整参数空间上运行单个统计时序分析。 统计时间分析的结果预计为所选角。 在具有最差松弛度的角落上进行定时关闭。

公开(公告)号：US08122409B2

公开(公告)日：2012-02-21

申请号：US11869306

申请日：2007-10-09

申请人： David E. Lackey ,  Chandramouli Visweswariah ,  Paul S. Zuchowski

发明人： David E. Lackey ,  Chandramouli Visweswariah ,  Paul S. Zuchowski

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F17/5031 ,  G01R31/318307 ,  G01R31/318364

摘要： A method, system, and integrated circuit including selectively added timing margin. The method, for integrating statistical timing and automatic test pattern generation (ATPG) to selectively add timing margin in an integrated circuit, includes identifying, while a chip is in design, paths that are unable to be robustly tested “at speed” during manufacturing test, running statistical timing to calculate a margin to be applied to the paths, updating design specifications for margin to be applied to the paths, and optimizing chip logic based on updated design specifications.

摘要翻译： 一种方法，系统和集成电路，包括选择性地添加定时裕度。 用于集成统计时序和自动测试模式生成（ATPG）以在集成电路中选择性地添加时序裕度的方法包括在芯片设计时识别在制造测试期间“以速度”无法被鲁棒测试的路径 ，运行统计计时，计算要应用于路径的余量，更新要应用于路径的余量的设计规范，以及基于更新的设计规范优化芯片逻辑。

公开(公告)号：US08112735B2

公开(公告)日：2012-02-07

申请号：US12020879

申请日：2008-01-28

申请人： Kerim Kalafala ,  Vasant Rao ,  Chandramouli Visweswariah

发明人： Kerim Kalafala ,  Vasant Rao ,  Chandramouli Visweswariah

IPC分类号： G06F17/50 ,  G06F13/00

CPC分类号： G06F17/5031 ,  G06K9/6226 ,  G06K9/6247

摘要： A computer system for partitioning the columns of a matrix A. The computer system includes a processor and a memory unit coupled to the processor. Program code in the memory unit, when executed by the processor, implements the method. Matrix A is provided in a memory device and has n columns and m rows; wherein n is an integer of at least 3; and wherein m is an integer of at least 1. The n columns is partitioned into a closed group of p clusters, p being a positive integer of at least 2 and less than n. The partitioning includes an affinity -based merging of clusters of pairs of clusters of the matrix A based on an affinity between the clusters in each pair of clusters being merged. Each cluster consists of one or more columns of matrix A. The p clusters are stored in a computer-readable storage device.

摘要翻译： 一种用于分割矩阵A的列的计算机系统。计算机系统包括处理器和耦合到处理器的存储器单元。 当处理器执行时，存储器单元中的程序代码实现该方法。 矩阵A在存储器件中提供并具有n列和m行; 其中n为至少3的整数; 并且其中m是至少为1的整数。所述n列被划分成闭合的p个簇，p是至少为2且小于n的正整数。 分割包括基于在被合并的每对群集中的群集之间的亲和度的矩阵A的聚类对的基于亲和度的合并。 每个簇由矩阵A的一个或多个列组成.P个簇存储在计算机可读存储设备中。

公开(公告)号：US08086976B2

公开(公告)日：2011-12-27

申请号：US12121023

申请日：2008-05-15

申请人： Jeffrey G. Hemmett ,  Chandramouli Visweswariah ,  Vladimir Zolotov

发明人： Jeffrey G. Hemmett ,  Chandramouli Visweswariah ,  Vladimir Zolotov

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F17/5031 ,  G06F2217/84

摘要： Methods for statistical slew propagation in static statistical timing analysis. The method includes projecting a canonical approximation of an input slew over a timing path to a first corner and using the projected input slew to calculate a delay and an output slew at the first corner. The method further includes perturbing the canonical approximation of the input slew to a different corner, calculating a delay and an output slew at the different corner using the perturbed input slew canonical, and determining a sensitivity of the delay and the output slew to a plurality of parameters, simultaneous with implicit sensitivity calculations to the input slew, with finite difference calculations between the first corner and perturbed data.

摘要翻译： 静态统计时序分析中统计转换传播的方法。 该方法包括将定时路径上的输入转换的规范近似投影到第一角，并且使用投影输入转换来计算在第一角处的延迟和输出。 该方法进一步包括将输入转换的规范近似扰乱到不同的角，使用干扰的输入转换来计算延迟和在不同角上的输出转换，并且将延迟和输出转换的灵敏度确定为多个 参数，同时与隐式灵敏度计算到输入转换，在第一个角和扰动数据之间进行有限差分计算。

公开(公告)号：US08056035B2

公开(公告)日：2011-11-08

申请号：US12132636

申请日：2008-06-04

申请人： Nathan C. Buck ,  Brian M. Dreibelbis ,  John P. Dubuque ,  Eric A. Foreman ,  Peter A. Habitz ,  David J. Hathaway ,  Gregory M. Schaeffer ,  Chandramouli Visweswariah

发明人： Nathan C. Buck ,  Brian M. Dreibelbis ,  John P. Dubuque ,  Eric A. Foreman ,  Peter A. Habitz ,  David J. Hathaway ,  Gregory M. Schaeffer ,  Chandramouli Visweswariah

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F2217/82

摘要： A method of performing statistical timing analysis of a logic design, including effects of signal coupling, includes performing a deterministic analysis to determine deterministic coupling information for at least one aggressor/victim net pair of the logic design. Additionally, the method includes performing a statistical timing analysis in which the deterministic coupling information for the at least one aggressor/victim net pair is combined with statistical values of the statistical timing analysis to determine a statistical effective capacitance of a victim of the aggressor/victim net pair. Furthermore, the method includes using the statistical effective capacitance to determine timing data used in the statistical timing analysis.

摘要翻译： 执行包括信号耦合效应的逻辑设计的统计定时分析的方法包括执行确定性分析以确定逻辑设计的至少一个攻击者/受害者网对的确定性耦合信息。 另外，该方法包括执行统计时序分析，其中至少一个攻击者/受害者网络对的确定性耦合信息与统计时间分析的统计值相结合，以确定攻击者/受害者的受害者的统计有效电容 净对。 此外，该方法包括使用统计有效电容来确定在统计时序分析中使用的定时数据。

公开(公告)号：US08015525B2

公开(公告)日：2011-09-06

申请号：US12114203

申请日：2008-05-02

申请人： Hongliang Chang ,  Sambasivan Narayan ,  Chandramouli Visweswariah ,  Vladimir Zolotov

发明人： Hongliang Chang ,  Sambasivan Narayan ,  Chandramouli Visweswariah ,  Vladimir Zolotov

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F17/5031

摘要： There is provided a system and method for statistical timing analysis and optimization of an electrical circuit having two or more digital elements. The system includes at least one parameter input and a statistical static timing analyzer and electrical circuit optimizer. The at least one parameter input is for receiving parameters of the electrical circuit. At least one of the parameters has at least one of a non-Gaussian probability distribution and a non-linear delay effect. The statistical static timing analyzer and electrical circuit optimizer is for calculating at least one of a signal arrival time and a signal required time for the electrical circuit using the at least one parameter and for modifying a component size of the electrical circuit to alter gate timing characteristics of the electrical circuit based upon the at least one of the signal arrival time and the signal required time.

摘要翻译： 提供了一种用于具有两个或多个数字元件的电路的统计时序分析和优化的系统和方法。 该系统包括至少一个参数输入和统计静态时序分析器和电路优化器。 至少一个参数输入用于接收电路的参数。 至少一个参数具有非高斯概率分布和非线性延迟效应中的至少一个。 统计静态时序分析器和电路优化器用于使用至少一个参数来计算电路的信号到达时间和信号所需时间中的至少一个，并且用于修改电路的组件尺寸以改变门时序特性 基于信号到达时间和信号所需时间中的至少一个。

公开(公告)号：US08010921B2

公开(公告)日：2011-08-30

申请号：US12209461

申请日：2008-09-12

申请人： Chandramouli Visweswariah

发明人： Chandramouli Visweswariah

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： The present invention is a system and method for statistical or probabilistic static timing analysis of digital circuits, taking into account statistical delay variations. The delay of each gate or wire is assumed to consist of a nominal portion, a correlated random portion that is parameterized by each of the sources of variation and an independent random portion. Arrival times and required arrival times are propagated as parameterized random variables while taking correlations into account. Both early mode and late mode timing are included; both combinational and sequential circuits are handled; static CMOS as well as dynamic logic families are accommodated. The timing analysis complexity is linear in the size of the graph and the number of sources of variation. The result is a timing report in which all timing quantities such as arrival times and slacks are reported as probability distributions in a parameterized form.

摘要翻译： 本发明是考虑到统计延迟变化的数字电路的统计或概率静态时序分析的系统和方法。 假设每个门或线的延迟由标称部分，由每个变化源参数化的相关随机部分和独立的随机部分组成。 考虑到相关性，到达时间和所需到达时间作为参数化随机变量传播。 包括早期模式和晚期模式时序; 处理组合和顺序电路; 静态CMOS以及动态逻辑系列。 时间分析复杂度在图形的大小和变异的数量上是线性的。 结果是定时报告，其中所有定时量（如到达时间和休息）以参数化形式报告为概率分布。

公开(公告)号：US20110191730A1

公开(公告)日：2011-08-04

申请号：US12696186

申请日：2010-01-29

申请人： Chandramouli Visweswariah ,  Jinjun Xiong ,  Vladimir P. Zolotov

发明人： Chandramouli Visweswariah ,  Jinjun Xiong ,  Vladimir P. Zolotov

IPC分类号： G06F17/50

CPC分类号： G06F17/50

摘要： Solutions for ordering of statistical correlated quantities are disclosed. In one aspect, a method includes timing a plurality of paths in an integrated circuit to determine a set of timing quantities associated with each of the plurality of paths; determining a most critical timing quantity in the set of timing quantities; forming a tiered timing quantity arrangement for ordering a plurality of timing quantities in the set of timing quantities; removing the most critical timing quantity from the set of timing quantities and placing the most critical timing quantity in an uppermost available tier of the tiered timing quantity arrangement; and repeating the determining, forming and removing for the set of timing quantities excluding the removed most critical timing quantity.

摘要翻译： 公布统计相关数量排序的解决方案。 在一个方面，一种方法包括对集成电路中的多个路径进行定时以确定与多个路径中的每一条相关联的一组定时量; 确定所述一组定时数量中最关键的定时数量; 形成用于在所述一组定时量中排序多个定时量的分层定时量排列; 从所述定时量集合中去除最关键的定时数量，并将最关键的定时数量置于分层定时数量排列的最上层可用层; 并且重复确定，形成和去除不包括去除的最关键定时量的一组定时量。

公开(公告)号：US20110106497A1

公开(公告)日：2011-05-05

申请号：US12610291

申请日：2009-10-31

申请人： Chandramouli Visweswariah ,  Jinjun Xiong ,  Vladimir Zolotov

发明人： Chandramouli Visweswariah ,  Jinjun Xiong ,  Vladimir Zolotov

IPC分类号： G21C17/00

CPC分类号： G06F17/5045 ,  G06F2217/10 ,  G06F2217/82

摘要： Techniques for improving parametric chip yield of manufactured chips are provided. In one aspect, a method for optimizing parametric chip yield is provided. The method includes the following steps. Parametric chip yield is computed based on performance and power consumption of a plurality of manufactured chips subject to a given voltage binning scheme. It is then determined whether the parametric chip yield computed is optimal. If the parametric chip yield is not optimal, the voltage binning scheme is altered and the compute and determine steps are repeated. Otherwise the binning scheme is left unaltered.

摘要翻译： 提供了用于提高制造芯片的参数芯片产量的技术。 在一个方面，提供了一种用于优化参数芯片产量的方法。 该方法包括以下步骤。 基于经受给定电压合并方案的多个制造的芯片的性能和功耗来计算参数芯片产量。 然后确定计算的参数芯片产量是否是最佳的。 如果参数芯片产量不是最优的，则改变电压组合方案，并重复计算和确定步骤。 否则，binning方案保持不变。