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1.发明授权Method and system for analyzing cross-talk coupling noise events in block-based statistical static timing 有权在基于块的统计静态时序中分析串扰耦合噪声事件的方法和系统公开(公告)号：US08056035B2
公开(公告)日：2011-11-08
申请号：US12132636
申请日：2008-06-04
申请人： Nathan C. Buck , Brian M. Dreibelbis , John P. Dubuque , Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Gregory M. Schaeffer , Chandramouli Visweswariah
发明人： Nathan C. Buck , Brian M. Dreibelbis , John P. Dubuque , Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Gregory M. Schaeffer , Chandramouli Visweswariah
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/82
摘要： A method of performing statistical timing analysis of a logic design, including effects of signal coupling, includes performing a deterministic analysis to determine deterministic coupling information for at least one aggressor/victim net pair of the logic design. Additionally, the method includes performing a statistical timing analysis in which the deterministic coupling information for the at least one aggressor/victim net pair is combined with statistical values of the statistical timing analysis to determine a statistical effective capacitance of a victim of the aggressor/victim net pair. Furthermore, the method includes using the statistical effective capacitance to determine timing data used in the statistical timing analysis.
摘要翻译： 执行包括信号耦合效应的逻辑设计的统计定时分析的方法包括执行确定性分析以确定逻辑设计的至少一个攻击者/受害者网对的确定性耦合信息。 另外，该方法包括执行统计时序分析，其中至少一个攻击者/受害者网络对的确定性耦合信息与统计时间分析的统计值相结合，以确定攻击者/受害者的受害者的统计有效电容 净对。 此外，该方法包括使用统计有效电容来确定在统计时序分析中使用的定时数据。
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2.发明申请METHOD AND SYSTEM FOR ANALYZING CROSS-TALK COUPLING NOISE EVENTS IN BLOCK-BASED STATISTICAL STATIC TIMING 有权基于块状统计静态时序分析交叉口耦合噪声事件的方法与系统公开(公告)号：US20090307645A1
公开(公告)日：2009-12-10
申请号：US12132636
申请日：2008-06-04
申请人： Nathan C. Buck , Brian M. Dreibelbis , John P. Dubuque , Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Gregory M. Schaeffer , Chandramouli Visweswariah
发明人： Nathan C. Buck , Brian M. Dreibelbis , John P. Dubuque , Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Gregory M. Schaeffer , Chandramouli Visweswariah
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/82
摘要： A method of performing statistical timing analysis of a logic design, including effects of signal coupling, includes performing a deterministic analysis to determine deterministic coupling information for at least one aggressor/victim net pair of the logic design. Additionally, the method includes performing a statistical timing analysis in which the deterministic coupling information for the at least one aggressor/victim net pair is combined with statistical values of the statistical timing analysis to determine a statistical effective capacitance of a victim of the aggressor/victim net pair. Furthermore, the method includes using the statistical effective capacitance to determine timing data used in the statistical timing analysis.
摘要翻译： 执行包括信号耦合效应的逻辑设计的统计定时分析的方法包括执行确定性分析以确定逻辑设计的至少一个攻击者/受害者网对的确定性耦合信息。 另外，该方法包括执行统计时序分析，其中至少一个攻击者/受害者网络对的确定性耦合信息与统计时间分析的统计值相结合，以确定攻击者/受害者的受害者的统计有效电容 净对。 此外，该方法包括使用统计有效电容来确定在统计时序分析中使用的定时数据。
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3.发明申请TIMING CLOSURE USING MULTIPLE TIMING RUNS WHICH DISTRIBUTE THE FREQUENCY OF IDENTIFIED FAILS PER TIMING CORNER 审中-公开使用多个时序的时序关闭，分配每个时间角的识别失败的频率公开(公告)号：US20090210839A1
公开(公告)日：2009-08-20
申请号：US12031106
申请日：2008-02-14
申请人： Nathan C. Buck , John P. Dubuque , Eric A. Foreman , Peter A. Habitz , Kerim Kalafala , Gregory M. Schaeffer , Chandramouli Visweswariah
发明人： Nathan C. Buck , John P. Dubuque , Eric A. Foreman , Peter A. Habitz , Kerim Kalafala , Gregory M. Schaeffer , Chandramouli Visweswariah
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/84
摘要： A method of timing closure for integrated circuit designs uses multiple timing runs which distribute the frequency of identified fails per timing corner (between starting timing corners and remaining timing corners) to maximize efficiency in timing analysis. More specifically, the method closes timing for a chosen set of starting timing corners, verifies the remaining timing corners are orthogonal to the starting timing corners, closes timing for the remaining timing corners using multi-corner analysis, and verifies that all timing corners have positive slack margin.
摘要翻译： 用于集成电路设计的定时闭合方法使用多个定时运行，其分配每个定时角点（在起始时间角和剩余时间角之间）识别的故障的频率，以最大化定时分析的效率。 更具体地，该方法关闭所选择的一组起始定时角的定时，验证剩余的定时角与起始正时角正交，关闭使用多角分析的剩余定时角的定时，并且验证所有定时角均为正 松弛边缘
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公开(公告)号：US07181711B2
公开(公告)日：2007-02-20
申请号：US10908101
申请日：2005-04-27
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A system and method of performing microelectronic chip timing analysis, wherein the method comprises identifying failing timing paths in a chip; prioritizing the failing timing paths in the chip according to a size of random noise events occurring in each timing path; attributing a slack credit statistic for all but highest order random noise events occurring in each timing path; and calculating a worst case timing path scenario based on the prioritized failing timing paths and the slack credit statistic. Preferably, the random noise events comprise non-clock events. Moreover, the random noise events may comprise victim/aggressor net groups belonging to different regularity groups. Preferably, the size of random noise events comprises coupled noise delta delays due to the random noise events occurring in the chip.
摘要翻译： 一种执行微电子芯片定时分析的系统和方法，其中所述方法包括识别芯片中的故障定时路径; 根据每个定时路径中发生的随机噪声事件的大小对芯片中的故障定时路径进行优先级排序; 归因于每个定时路径中发生的所有但最高阶随机噪声事件的松弛信用统计; 以及基于优先顺序的故障定时路径和松弛信用统计量来计算最坏情况的定时路径情景。 优选地，随机噪声事件包括非时钟事件。 此外，随机噪声事件可以包括属于不同规则组的受害者/侵略者网络组。 优选地，由于芯片中发生的随机噪声事件，随机噪声事件的大小包括耦合的噪声增量延迟。
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公开(公告)号：US07750648B2
公开(公告)日：2010-07-06
申请号：US12059275
申请日：2008-03-31
申请人： Eric A. Foreman , Peter A. Habitz , Mark R. Lasher , William J. Livingstone , Gregory M. Schaeffer
发明人： Eric A. Foreman , Peter A. Habitz , Mark R. Lasher , William J. Livingstone , Gregory M. Schaeffer
IPC分类号： G01R27/00
CPC分类号： G01R27/2611 , G01R27/28 , G06F17/5036 , G06F2217/84
摘要： A method of estimating an inductance delay includes determining a resistance-capacitance (RC) delay with resistances and capacitances of a network and estimating an inductance delay of the network by determining a propagation delay of an electromagnetic (EM) field across wires of the network. Additionally, the method includes determining if the RC delay is below a specified threshold and adding the estimated inductance delay to the RC delay to determine a total time to propagate voltage swings through the network if the RC delay is below the specified threshold.
摘要翻译： 估计电感延迟的方法包括通过确定网络的电线（EM）场的传播延迟来确定网络的电阻和电容的电阻 - 电容（RC）延迟并估计网络的电感延迟。 此外，该方法包括确定RC延迟是否低于指定的阈值，并将估计的电感延迟与RC延迟相加，以确定如果RC延迟低于指定阈值，则传播通过网络的电压摆幅的总时间。
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公开(公告)号：US20090243630A1
公开(公告)日：2009-10-01
申请号：US12059275
申请日：2008-03-31
申请人： Eric A. Foreman , Peter A. Habitz , Mark R. Lasher , William J. Livingstone , Gregory M. Schaeffer
发明人： Eric A. Foreman , Peter A. Habitz , Mark R. Lasher , William J. Livingstone , Gregory M. Schaeffer
IPC分类号： G01R27/28
CPC分类号： G01R27/2611 , G01R27/28 , G06F17/5036 , G06F2217/84
摘要： A method of estimating an inductance delay includes determining a resistance-capacitance (RC) delay with resistances and capacitances of a network and estimating an inductance delay of the network by determining a propagation delay of an electromagnetic (EM) field across wires of the network. Additionally, the method includes determining if the RC delay is below a specified threshold and adding the estimated inductance delay to the RC delay to determine a total time to propagate voltage swings through the network if the RC delay is below the specified threshold.
摘要翻译： 估计电感延迟的方法包括通过确定网络的电线（EM）场的传播延迟来确定网络的电阻和电容的电阻 - 电容（RC）延迟并估计网络的电感延迟。 此外，该方法包括确定RC延迟是否低于指定的阈值，并将估计的电感延迟与RC延迟相加，以确定如果RC延迟低于指定阈值，则传播通过网络的电压摆幅的总时间。
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7.发明授权Method and apparatus for static timing analysis in the presence of a coupling event and process variation 失效在存在耦合事件和过程变化的情况下进行静态时序分析的方法和装置公开(公告)号：US07739640B2
公开(公告)日：2010-06-15
申请号：US11622979
申请日：2007-01-12
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/84
摘要： In one embodiment, the invention is a method and apparatus for static timing analysis in the presence of a coupling event and process variation. One embodiment of a method for computing a statistical change in delay and slew due to a coupling event between two adjacent nets in an integrated circuit design includes conducting a statistical timing analysis of the integrated circuit design, computing a statistical overlap window between the adjacent nets, where the statistical timing window represents a period of time during which signals on the adjacent nets can switch contemporaneously and computing the statistical change of delay due to the coupling event, in accordance with the statistical overlap window.
摘要翻译： 在一个实施例中，本发明是在存在耦合事件和过程变化的情况下用于静态时序分析的方法和装置。 用于计算由于集成电路设计中的两个相邻网络之间的耦合事件而导致的延迟和转换的统计变化的方法的一个实施例包括进行集成电路设计的统计时序分析，计算相邻网络之间的统计重叠窗口， 其中统计定时窗口表示相邻网络上的信号可以同时切换的时间段，并且根据统计重叠窗口计算由于耦合事件引起的延迟的统计变化。
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8.发明申请METHOD AND APPARATUS FOR STATIC TIMING ANALYSIS IN THE PRESENCE OF A COUPLING EVENT AND PROCESS VARIATION 失效联系事件和过程变化存在的静态时序分析方法与装置公开(公告)号：US20080172642A1
公开(公告)日：2008-07-17
申请号：US11622979
申请日：2007-01-12
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/84
摘要： In one embodiment, the invention is a method and apparatus for static timing analysis in the presence of a coupling event and process variation. One embodiment of a method for computing a statistical change in delay and slew due to a coupling event between two adjacent nets in an integrated circuit design includes conducting a statistical timing analysis of the integrated circuit design, computing a statistical overlap window between the adjacent nets, where the statistical timing window represents a period of time during which signals on the adjacent nets can switch contemporaneously and computing the statistical change of delay due to the coupling event, in accordance with the statistical overlap window.
摘要翻译： 在一个实施例中，本发明是在存在耦合事件和过程变化的情况下用于静态时序分析的方法和装置。 用于计算由于集成电路设计中的两个相邻网络之间的耦合事件而导致的延迟和转换的统计变化的方法的一个实施例包括进行集成电路设计的统计时序分析，计算相邻网络之间的统计重叠窗口， 其中统计定时窗口表示相邻网络上的信号可以同时切换的时间段，并且根据统计重叠窗口计算由于耦合事件引起的延迟的统计变化。
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9.发明授权Method for fast incremental calculation of an impact of coupled noise on timing 有权耦合噪声对定时影响的快速增量计算方法公开(公告)号：US07398491B2
公开(公告)日：2008-07-08
申请号：US11420529
申请日：2006-05-26
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5036
摘要： A method for incrementally calculating the impact of coupling noise on the timing of an integrated circuit (IC) having a plurality of logic stages by performing an initial timing analysis on the IC to provide a first determination of the impact of coupling noise on the timing. One or more design changes to the IC are then performed. In response to the design change, the impact of the coupling noise to the timing is calculated on the logic stage where the change was made and on the logic stages downstream thereof. The results of the calculations are then inputted to a timing analysis tool to adjust the delay and slew of each logic stage where the design change was made and to the logic stages downstream thereof.
摘要翻译： 一种用于通过对IC执行初始定时分析来递增地计算耦合噪声对具有多个逻辑级的集成电路（IC）的定时的影响的方法，以提供耦合噪声对定时的影响的第一确定。 然后执行对IC的一个或多个设计更改。 响应于设计变化，耦合噪声对定时的影响是在进行改变的逻辑阶段和下游的逻辑级上计算的。 然后将计算结果输入到定时分析工具，以调整进行设计更改的每个逻辑级的延迟和转换以及其下游的逻辑级。
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10.发明申请公开(公告)号：US20070277131A1
公开(公告)日：2007-11-29
申请号：US11420529
申请日：2006-05-26
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5036
摘要： A method for incrementally calculating the impact of coupling noise on the timing of an integrated circuit (IC) having a plurality of logic stages by performing an initial timing analysis on the IC to provide a first determination of the impact of coupling noise on the timing. One or more design changes to the IC are then performed. In response to the design change, the impact of the coupling noise to the timing is calculated on the logic stage where the change was made and on the logic stages downstream thereof. The results of the calculations are then inputted to a timing analysis tool to adjust the delay and slew of each logic stage where the design change was made and to the logic stages downstream thereof.
摘要翻译： 一种用于通过对IC执行初始定时分析来递增地计算耦合噪声对具有多个逻辑级的集成电路（IC）的定时的影响的方法，以提供耦合噪声对定时的影响的第一确定。 然后执行对IC的一个或多个设计更改。 响应于设计变化，耦合噪声对定时的影响是在进行改变的逻辑阶段和下游的逻辑级上计算的。 然后将计算结果输入到定时分析工具，以调整进行设计更改的每个逻辑级的延迟和转换以及其下游的逻辑级。
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