公开(公告)号：US06337806B1

公开(公告)日：2002-01-08

申请号：US09604635

申请日：2000-06-27

Applicant: Hong-goo Yoon ,  Jeong-seok Lee

Inventor： Hong-goo Yoon ,  Jeong-seok Lee

IPC: G11C1124

CPC classification number: G11C7/1006 ,  G11C2207/104

Abstract: A semiconductor device having data multiplexing and data masking functions is provided. The semiconductor device includes a dynamic random access memory (DRAM) cell array for inputting or outputting M×N data signals in parallel, a logic circuit having a control function, and a memory unit connected between the DRAM cell array and the logic circuit. The memory unit transmits or receives M×N data signals to or from the DRAM cell array and transmits or receives M data signals to or from the logic circuit, in response to an address signal input from the outside. The memory unit includes at least M memory blocks. Each memory block receives N data signals from the DRAM cell array and transmits at least one data signal to the logic circuit, and receives at least one data signal from the logic circuits and transmits N data signals to the DRAM cell array. A write/read word line driver connects to the at least M memory blocks. The write/read word line driver decodes the address signal, selectively controls writes of data input from the DRAM cell array and the logic circuit to each memory block, and selectively controls reads of data stored in each memory block to transmit the data to the DRAM cell and the logic circuit.

Abstract translation: 提供了具有数据复用和数据屏蔽功能的半导体器件。 半导体器件包括用于并行输入或输出M×N数据信号的动态随机存取存储器（DRAM）单元阵列，具有控制功能的逻辑电路以及连接在DRAM单元阵列与逻辑电路之间的存储单元。 存储单元响应于从外部输入的地址信号，向/从DRAM单元阵列发送或接收M×N数据信号，并向逻辑电路发送或接收M个数据信号。 存储器单元至少包括M个存储器块。 每个存储器块从DRAM单元阵列接收N个数据信号，并将至少一个数据信号发送到逻辑电路，并从逻辑电路接收至少一个数据信号，并将N个数据信号发送到DRAM单元阵列。 写入/读取字线驱动器连接至少M个存储器块。 写/读字线驱动器解码地址信号，选择性地控制从DRAM单元阵列和逻辑电路输入到每个存储器块的数据写入，并且有选择地控制存储在每个存储器块中的数据的读取以将数据发送到DRAM 单元和逻辑电路。