公开(公告)号：US11126714B2

公开(公告)日：2021-09-21

申请号：US16149297

申请日：2018-10-02

Applicant: Arm Limited

Inventor： Alastair David Reid ,  Dominic Phillip Mulligan ,  Milosch Meriac ,  Matthias Lothar Boettcher ,  Nathan Yong Seng Chong ,  Ian Michael Caulfield ,  Peter Richard Greenhalgh ,  Frederic Claude Marie Piry ,  Albin Pierrick Tonnerre ,  Thomas Christopher Grocutt ,  Yasuo Ishii

IPC: G06F21/55 ,  H04L9/06 ,  G06F9/38 ,  G06F12/10 ,  G06F21/53 ,  G06F21/78

Abstract: A data processing apparatus comprises branch prediction circuitry adapted to store at least one branch prediction state entry in relation to a stream of instructions, input circuitry to receive at least one input to generate a new branch prediction state entry, wherein the at least one input comprises a plurality of bits; and coding circuitry adapted to perform an encoding operation to encode at least some of the plurality of bits based on a value associated with a current execution environment in which the stream of instructions is being executed. This guards against potential attacks which exploit the ability for branch prediction entries trained by one execution environment to be used by another execution environment as a basis for branch predictions.

公开(公告)号：US10810094B2

公开(公告)日：2020-10-20

申请号：US16014154

申请日：2018-06-21

Applicant: Arm Limited

Inventor： Milosch Meriac ,  Xabier Iturbe ,  Emre Ozer ,  Balaji Venu ,  Shidhartha Das

IPC: G06F11/00 ,  G06F11/20 ,  G06F11/16 ,  G06F11/14 ,  G06F11/30 ,  G06F21/50

Abstract: Examples of the present disclosure relate to a method for anomaly response in a system on chip. The method comprises measuring a magnitude of a transient anomaly event in an operating condition of the system on chip. Based on the magnitude it is determined, for each of a plurality of components of the system on chip, an indication of susceptibility of that component to an anomaly event of the measured magnitude. Based on the determined indications of susceptibility for each of the plurality of components, an anomaly response action is determined. The method then comprises performing the anomaly response action.

公开(公告)号：US10725873B2

公开(公告)日：2020-07-28

申请号：US15995469

申请日：2018-06-01

Applicant: Arm Limited

Inventor： Milosch Meriac ,  Shidhartha Das

IPC: G06F11/00 ,  G06F11/16 ,  G06F1/12

Abstract: The present techniques generally relate to a method of monitoring for a fault event in a lockstep processing system having a plurality of cores configured to operate in lockstep, the method having: power gating, for a period of time, a subset of cores of the plurality of cores from a first power source and providing power to the subset of cores from a second power source for the period of time; processing, at each of the cores of the plurality of cores, one or more instructions; providing an output from each core of the plurality of cores to error detection circuitry to monitor for the fault event, the output from each core based on or in response to processing the one or more instructions during the period of time.