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公开(公告)号:US20200218625A1
公开(公告)日:2020-07-09
申请号:US16823180
申请日:2020-03-18
Applicant: Arm Limited
Inventor: Emre Ozer , Xabier Iturbe , Balaji Venu
Abstract: Briefly, example methods, apparatuses, and/or articles of manufacture are disclosed that may be implemented, in whole or in part, to determine indicators of potential errors in a multi-processing core lockstep computing device comprising a plurality of processing cores, based, at least in part, on observations of output signals generated by at least two processing cores of the plurality of processing cores. A built-in self-test (BIST) procedure may then be based, at least in part, on the determining indicators.
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公开(公告)号:US11061852B2
公开(公告)日:2021-07-13
申请号:US16645993
申请日:2018-09-25
Applicant: Arm Limited
Inventor: Mbou Eyole , Emre Ozer , Xabier Iturbe , Shidhartha Das
IPC: G11C7/00 , G06F15/78 , G11C14/00 , H03K19/17728 , G06F15/76
Abstract: A method of reconfiguration and a reconfigurable circuit architecture comprising a configurable volatile storage circuit and Non-Volatile Memory circuit elements; wherein the Non-Volatile memory circuit elements store multiple bit states for re-configuration, the multiple bit states being read from the Non-Volatile memory circuit elements and written into the configurable volatile storage circuit for reconfiguration. The Non-Volatile Memory circuit elements and the configurable volatile storage circuit are provided on a common die.
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公开(公告)号:US20200226095A1
公开(公告)日:2020-07-16
申请号:US16645993
申请日:2018-09-25
Applicant: Arm Limited
Inventor: Mbou Eyole , Emre Ozer , Xabier Iturbe , Shidhartha Das
IPC: G06F15/78 , G11C14/00 , H03K19/17728
Abstract: A method of reconfiguration and a reconfigurable circuit architecture comprising a configurable volatile storage circuit and Non-Volatile Memory circuit elements; wherein the Non-Volatile memory circuit elements store multiple bit states for re-configuration, the multiple bit states being read from the Non-Volatile memory circuit elements and written into the configurable volatile storage circuit for reconfiguration. The Non-Volatile Memory circuit elements and the configurable volatile storage circuit are provided on a common die.
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公开(公告)号:US10657010B2
公开(公告)日:2020-05-19
申请号:US15800145
申请日:2017-11-01
Applicant: ARM Limited
Inventor: Xabier Iturbe , Emre Ozer , Balaji Venu
Abstract: An apparatus 2 comprises at least three processing circuits 4 to perform redundant processing of a common thread of program instructions. Error detection circuitry 16 is provided comprising a number of comparators 22 for detecting a mismatch between signals on corresponding signal nodes 20 in the processing circuits 4. When a comparator 22 detects a mismatch, this triggers a recovery process. The error detection circuitry 16 generates an unresolvable error signal 36 indicating that a detected area is unresolvable by the recovery process when, during the recovery process, a mismatch is detected by one of the proper subset 34 of the comparators 22. By considering fewer comparators 22 during the recovery process than during normal operation, the chances of unrecoverable errors being detected can be reduced, increasing system availability.
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公开(公告)号:US10303566B2
公开(公告)日:2019-05-28
申请号:US15645053
申请日:2017-07-10
Applicant: ARM LIMITED
Inventor: Emre Özer , Balaji Venu , Xabier Iturbe , Antony John Penton
Abstract: An apparatus and method are provided for checking output data during redundant execution of instructions. The apparatus has first processing circuitry for executing a sequence of instructions and second processing circuitry for redundantly executing the sequence of instructions. Error code generation circuitry is used to generate an error code from the first output data generated by the first processing circuitry. Error checking circuitry then uses that error code to perform an error checking operation on redundant output data from the second processing circuitry. As a result of the error checking operation, the error checking circuitry then generates a comparison indication signal to indicate that the first output data differs from the redundant output data when the error checking operation detects an error. This provides a very efficient mechanism for implicitly comparing the output data from the first processing circuitry and the second processing circuitry during redundant execution.
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公开(公告)号:US11494256B2
公开(公告)日:2022-11-08
申请号:US17261217
申请日:2019-06-06
Applicant: Arm Limited
Inventor: Milosch Meriac , Emre Özer , Xabier Iturbe , Balaji Venu , Shidhartha Das
Abstract: An apparatus comprises a plurality of redundant processing units to perform data processing redundantly in lockstep; common mode fault detection circuitry to detect an event indicative of a potential common mode fault affecting each of the plurality of redundant processing units; a memory shared between the plurality of redundant processing units; and memory checking circuitry to perform a memory scanning operation to scan at least part of the memory for errors; in which the memory checking circuitry performs the memory scanning operation in response to a common mode fault signal generated by the common mode fault detection circuitry indicating that the event indicative of a potential common mode fault has been detected.
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公开(公告)号:US10810094B2
公开(公告)日:2020-10-20
申请号:US16014154
申请日:2018-06-21
Applicant: Arm Limited
Inventor: Milosch Meriac , Xabier Iturbe , Emre Ozer , Balaji Venu , Shidhartha Das
Abstract: Examples of the present disclosure relate to a method for anomaly response in a system on chip. The method comprises measuring a magnitude of a transient anomaly event in an operating condition of the system on chip. Based on the magnitude it is determined, for each of a plurality of components of the system on chip, an indication of susceptibility of that component to an anomaly event of the measured magnitude. Based on the determined indications of susceptibility for each of the plurality of components, an anomaly response action is determined. The method then comprises performing the anomaly response action.
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公开(公告)号:US10523186B1
公开(公告)日:2019-12-31
申请号:US16206234
申请日:2018-11-30
Applicant: Arm Limited
Inventor: Balaji Venu , Reiley Jeyapaul , Xabier Iturbe , Matthew James Horsnell , David Michael Gilday
IPC: G06F17/50 , G06F9/455 , H03K3/037 , G01R31/3183
Abstract: An apparatus is provided comprising receiving circuitry to receive a representation of a circuit comprising a plurality of flops. Categorisation circuitry determines data dependencies between the flops from the representation and generates a categorisation of the flops into one of at least: a vulnerable category, a conditional category, and an isolated category, in dependence on the data dependencies. The categorisation indicates the vulnerability of the flops to transient errors. Output circuitry outputs the categorisation of the flops. The conditional category comprises those of the flops whose change in value is indicated by a change in a value in a corresponding flop in the flops or corresponding signal. The vulnerable category comprises those of the flops that are absent from the conditional category and whose change in value is affected by one of the flops or a signal and the isolated category comprises the flops that are absent from the conditional category and that are absent from the vulnerable category.
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公开(公告)号:US10185635B2
公开(公告)日:2019-01-22
申请号:US15463066
申请日:2017-03-20
Applicant: ARM Limited
Inventor: Balaji Venu , Xabier Iturbe , Emre Özer
Abstract: An apparatus comprises at least three processing circuits to perform redundant processing of common program instructions. Error detection circuitry coupled to a plurality of signal nodes of each of said at least three processing circuits comprises comparison circuitry to detect a mismatch between signals on corresponding signal nodes in said at least three processing circuits, the plurality of signal nodes forming a first group of signal nodes and a second group of signal nodes. In response to the mismatch being detected in relation to corresponding signal nodes within the first group, the error detection circuitry is configured to generate a first trigger for a full recovery process for resolving an error detected for an erroneous processing circuit using state information derived from at least two other processing circuits. In response to the mismatch being detected in relation to corresponding signal nodes within the second group the error detection circuitry is configured to generate a second trigger for a targeted recovery process for a subset of components of the erroneous processing circuit. By implementing a targeted recovery process for a subset of components of an erroneous processing circuit a cheaper recovery process may be provided.
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公开(公告)号:US11176012B2
公开(公告)日:2021-11-16
申请号:US16823180
申请日:2020-03-18
Applicant: Arm Limited
Inventor: Emre Ozer , Xabier Iturbe , Balaji Venu
Abstract: Briefly, example methods, apparatuses, and/or articles of manufacture are disclosed that may be implemented, in whole or in part, to determine indicators of potential errors in a multi-processing core lockstep computing device comprising a plurality of processing cores, based, at least in part, on observations of output signals generated by at least two processing cores of the plurality of processing cores. A built-in self-test (BIST) procedure may then be based, at least in part, on the determining indicators.
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