Shift register and driving method therefor, gate driver circuit and display apparatus

    公开(公告)号:US11308838B2

    公开(公告)日:2022-04-19

    申请号:US17051738

    申请日:2020-01-21

    Abstract: A shift register includes a first transistor, a second transistor, a pull-up node and a switch sub-circuit. A control electrode of the first transistor is connected to a signal input terminal, a first electrode of the first transistor is connected to a first voltage terminal, and a second electrode of the first transistor is connected to a first control node. A control electrode of the second transistor is connected to a reset signal terminal, a first electrode of the second transistor is connected to a second voltage terminal, and a second electrode of the second transistor is connected to the first control node. The switching sub-circuit is connected to the first control node and the pull-up node, and is configured to control a line between the first control node and the pull-up node to be closed and opened.

    SHIFT REGISTER UNIT AND METHOD FOR DRIVING THE SAME, GATE DRIVING CIRCUIT AND METHOD FOR DRIVING THE SAME, AND DISPLAY APPARATUS

    公开(公告)号:US20210209988A1

    公开(公告)日:2021-07-08

    申请号:US16769910

    申请日:2020-01-08

    Abstract: The present disclosure provides a shift register unit and a method for driving the same, a gate driving circuit and a method for driving the same, and a display apparatus. The shift register unit includes an input sub-circuit, a discharging control sub-circuit, a discharging sub-circuit, and an output sub-circuit. The input sub-circuit is configured to transmit an input signal at an input signal terminal to a first node under control of a voltage at a second node. The discharging control sub-circuit is configured to transmit a first clock signal at a first clock signal terminal to the second node under control of a voltage at the first node. The discharging sub-circuit is configured to transmit a first constant voltage signal at a first constant voltage signal terminal to an output signal terminal under control of the voltage at the second node. The output sub-circuit is configured to transmit a second clock signal at a second clock signal terminal to the output signal terminal under control of the voltage at the first node.

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