公开(公告)号：US20050060633A1

公开(公告)日：2005-03-17

申请号：US10922205

申请日：2004-08-19

申请人： Keshab Parhi ,  Junjin Kong

发明人： Keshab Parhi ,  Junjin Kong

IPC分类号： H03M13/03 ,  H03M13/41

CPC分类号： H03M13/3961 ,  H03M13/395 ,  H03M13/4107

摘要： Digital circuits and methods for designing digital circuits are presented. More particularly, the present invention relates to error correction circuits and methods in communications and other systems. In the present invention, a novel K-nested layered look-ahead method and its corresponding architecture, which combine K-trellis steps into one trellis step (where K is the encoder constraint length), are proposed for implementing low-latency high through-put rate Viterbi decoder circuits. The main idea of the present invention involves combining K-trellis steps as a pipeline structure and then combining the resulting look-ahead branch metrics as a tree structure in a layered manner to decrease the ACS precomputation latency of look-ahead Viterbi decoder circuits. The proposed method guarantees parallel paths between any two trellis states in the look-ahead trellises and distributes the add-compare-select (ACS) computations to all trellis layers. It leads to regular and simple architecture for the Viterbi decoding algorithm. The look-ahead ACS computation latency of the proposed method increases logarithmically with respect to the look-ahead step (M) divided by the encoder constraint length (K) as opposed to linearly as in prior work. The main advantage of this invention is that it has the least latency among all known look-ahead Viterbi decoder circuits for a given level of parallelism.

摘要翻译： 提出了数字电路和数字电路设计方法。 更具体地，本发明涉及通信和其他系统中的纠错电路和方法。 在本发明中，提出了一种新颖的K嵌套分层预先方法及其相应的体系结构，其将K-trellis步骤组合成一个网格步骤（其中K是编码器约束长度），用于实现低延迟高通/ 放码率维特比解码电路。 本发明的主要思想涉及将K-trellis步骤组合为流水线结构，然后以分层方式将所得到的预先分支量度作为树结构组合，以降低先行维特比解码器电路的ACS预计算延迟。 所提出的方法保证先行网格中的任何两个网格状态之间的并行路径，并将加法比较选择（ACS）计算分配给所有网格层。 它导致维特比解码算法的常规和简单的架构。 与先前的工作相比，所提出的方法的先行ACS计算等待时间相对于先行步长（M）除以编码器约束长度（K）而对数地增加。 本发明的主要优点在于，对于给定的并行水平，它在所有已知的提前维特比解码器电路中具有最小的等待时间。