公开(公告)号：US10084486B1

公开(公告)日：2018-09-25

申请号：US15720905

申请日：2017-09-29

申请人： Intel Corporation

发明人： Jianbin Zhu ,  Yi Zhou ,  Yuzhou Zhang ,  Yuan Li ,  Chuong Vu

IPC分类号： H04L5/12 ,  H04L23/02 ,  H03M13/29 ,  H04L1/00 ,  H03M13/39 ,  H03M13/00

CPC分类号： H03M13/2957 ,  H03M13/3905 ,  H03M13/3922 ,  H03M13/3927 ,  H03M13/395 ,  H03M13/3961 ,  H03M13/3972 ,  H03M13/6561 ,  H03M13/658 ,  H04L1/0055

摘要： A method for decoding a received code using a device that includes: an antenna for receiving a signal over a wireless channel, and instances of a Maximum-A-Posteriori (MAP) turbo decoder for decoding a segment of the received code, are disclosed. For example, the method, by forward and backward gamma engines, for each window, concurrently computes gamma branch metrics in forward and backward directions, respectively, by forward and backward state metric engines comprising respective lambda engines and coupled to the respective gamma engines, for each window, sequentially computes forward and backward state metrics, respectively, based on respective gamma branch metrics and respective initial values, by the lambda engines, determines Log Likelihood Ratios (LLRs) and soft decisions, and by a post-processor, computes extrinsic data based on the forward and backward state metrics for any subsequent iteration as at least a portion of the a-priori information and otherwise provides a decoded segment.

公开(公告)号：US09787331B1

公开(公告)日：2017-10-10

申请号：US15224939

申请日：2016-08-01

申请人： YUAN ZE UNIVERSITY

发明人： Cheng-Hung Lin ,  Tsung-Ju Hsieh

IPC分类号： H03M13/03 ,  H03M13/39 ,  H03M13/23 ,  H03M13/25 ,  H03M13/41

CPC分类号： H03M13/4161 ,  H03M13/3905 ,  H03M13/395

摘要： The present invention discloses a decoding path selection device for decoding codewords generated by convolutional codes or turbo codes encoders in error correction codes, the decoding path selection device comprising: a branch metrics calculation unit for receiving incoming signals and calculating branch metrics values; a programmable generalized trellis router for generating a decoding path control signal according to the turbo code or convolutional code specification employed by one of communications standards; a multiplexer for receiving the branch metrics values from the branch metrics calculation unit and the decoding path control signal from the programmable generalized trellis router and selecting a corresponding branch metrics value; a recursive calculation unit, connected after the multiplexer and for receiving the corresponding branch metrics value from the multiplexer; and an a-posteriori probability calculation unit, connected after the recursive calculation unit and for calculating a final decoding result.

公开(公告)号：US09189456B2

公开(公告)日：2015-11-17

申请号：US13916810

申请日：2013-06-13

申请人： Timothy D Anderson ,  Shriram D Moharil

发明人： Timothy D Anderson ,  Shriram D Moharil

IPC分类号： G06F7/50 ,  G06F17/12 ,  H03M13/39 ,  H03M13/41 ,  H03M13/00

CPC分类号： G06F17/12 ,  H03M13/3922 ,  H03M13/395 ,  H03M13/4107 ,  H03M13/6502 ,  H03M13/6511 ,  H03M13/6586

摘要： The present invention provides a means for optimization and re-use of hardware in the implementation of Viterbi and Turbo Decoders using carry save arithmetic. Successful provision for each target application requires that two main issues be confronted. These are: merging the computation of summation terms (a2−b2+c2) with (x2+y2+z2); and (a3+b3−c3) with (x3+y3+z3); implementing an efficient method of computing (a4−b4−c4); and merging this computation with (x4+y4+z4). The invention solves both of these issues and successfully merges the Viterbi instructions with a complete reuse of the hardware that is required for the implementation of Turbo instructions. The hardware required by both classes of instructions is optimized by efficiently employing carry save arithmetic.

摘要翻译： 本发明提供了一种用于在使用进位保存算术实现维特比和Turbo解码器中优化和重用硬件的手段。 每个目标申请的成功规定要求面对两个主要问题。 这些是：将求和项（a2-b2 + c2）与（x2 + y2 + z2）的计算合并; 和（a3 + b3-c3）与（x3 + y3 + z3） 实现有效的计算方法（a4-b4-c4）; 并将该计算与（x4 + y4 + z4）合并。 本发明解决了这两个问题，并且成功地将维特比指令与实现Turbo指令所需的硬件的完全重用相结合。 通过有效地采用进位保存算法来优化两类指令所需的硬件。

公开(公告)号：US08495455B1

公开(公告)日：2013-07-23

申请号：US13035698

申请日：2011-02-25

申请人： Tao Zhang ,  Jianbin Zhu ,  Yuan Li

发明人： Tao Zhang ,  Jianbin Zhu ,  Yuan Li

IPC分类号： H03M13/00

CPC分类号： G06F11/10 ,  H03M13/271 ,  H03M13/2714 ,  H03M13/2739 ,  H03M13/2957 ,  H03M13/395 ,  H03M13/3972 ,  H03M13/6505 ,  H03M13/6525 ,  H03M13/6561

摘要： According to some embodiments, a turbo decoder configured for High-Speed Packet Access (HSPA) and Long Term Evolution (LTE) is provided, comprising: a plurality of maximum a posteriori (MAP) engines; a plurality of extrinsic memory banks accessible by a MAP engine of the plurality of MAP engines; and wherein when the turbo decoder is operating in HSDPA mode the plurality of extrinsic memory banks is configured such that during a first half of a decoding iteration, the MAP engine is able to read a first dataset from and write second dataset to the plurality of extrinsic memory banks in natural row and column order, and during a second half of the decoding iteration, the MAP engine is able to read a third dataset from and write a fourth dataset to the plurality of extrinsic memory banks in a predetermined row and column order in accordance with an interleaver table using a read column buffer and a write column buffer.

摘要翻译： 根据一些实施例，提供了配置用于高速分组接入（HSPA）和长期演进（LTE）的turbo解码器，包括：多个最大后验（MAP）引擎; 由多个MAP引擎的MAP引擎访问的多个外部存储器组; 并且其中当所述turbo解码器以HSDPA模式操作时，所述多个非本征存储体被配置为使得在解码迭代的前半部分期间，MAP引擎能够从第二数据集读取第一数据集并将第二数据集写入到所述多个外部 存储器组以自然行和列顺序排列，并且在解码迭代的后半段期间，MAP引擎能够以预定的行和列顺序从第二数据集读取和写入第四数据集到多个外部存储体 根据使用读列缓冲器和写列缓冲器的交织器表。

公开(公告)号：US08407571B2

公开(公告)日：2013-03-26

申请号：US12547841

申请日：2009-08-26

申请人： Jonathan James Ashley ,  Kelly Knudson Fitzpatrick ,  Erich Franz Haratsch

发明人： Jonathan James Ashley ,  Kelly Knudson Fitzpatrick ,  Erich Franz Haratsch

IPC分类号： H03M13/00

CPC分类号： H03M13/4192 ,  H03M13/395 ,  H03M13/4153

摘要： Methods and apparatus are provided for performing SOVA detection at higher data rates than achievable with conventional designs. A received signal is processed by (i) determining at least three selection signals that define a plurality of paths through a multiple-step trellis into a given state, wherein a first of the plurality of paths is a winning path for each single-step-trellis period of a multiple-step-trellis cycle, a second path is a winning path for a first single-step-trellis period and is a losing path for a second single-step-trellis period of a multiple-step-trellis cycle and a third path is a losing path for a first single-step-trellis period and is a winning path for a second single-step-trellis period of a multiple-step-trellis cycle; and (ii) determining at least one reliability value (such as a reliability value for a bit decision associated with a maximum-likelihood path through the multiple-step trellis or a plurality of reliability values for each multiple-step-trellis cycle).

摘要翻译： 提供了用于以比常规设计可实现的更高数据速率执行SOVA检测的方法和装置。 接收到的信号通过以下步骤来处理：（i）确定至少三个选择信号，其将通过多步网格的多个路径定义到给定状态，其中多条路径中的第一条路径是用于每个单步路段的获胜路径， 多步骤格雷周期的网格周期，第二路径是第一单步网格周期的获胜路径，并且是多步骤网格周期的第二单步网格周期的丢失路径，并且 第三条路径是第一个单步网格周期的失败之路，是多阶段格雷周期的第二个单步阶段的获胜路径; 和（ii）确定至少一个可靠性值（诸如与通过多步网格的最大似然路径相关联的比特决定的可靠性值或每个多步网格周期的多个可靠性值）。

公开(公告)号：US08321770B2

公开(公告)日：2012-11-27

申请号：US12547862

申请日：2009-08-26

申请人： Kelly Knudson Fitzpatrick ,  Erich Franz Haratsch

发明人： Kelly Knudson Fitzpatrick ,  Erich Franz Haratsch

IPC分类号： H03M13/03

CPC分类号： H03M13/4192 ,  H03M13/395 ,  H03M13/4153

摘要： A path comparison unit is disclosed for determining paths in a trellis that compete with a survivor path. The disclosed path comparison unit comprises a first type functional unit comprising a multiplexer and a register to store one or more survivor bits associated with the survivor path; and at least two second type functional units, wherein each second type functional unit comprises a multiplexer and a logical circuit to compute at least one equivalence bit indicating whether the bit for a respective path and the bit for the survivor path are equivalent. Generally, the respective path is one or more of a win-lose path and a lose-win path.

摘要翻译： 公开了一种用于确定与幸存路径竞争的网格中的路径的路径比较单元。 所公开的路径比较单元包括第一类型功能单元，包括多路复用器和寄存器，用于存储与幸存路径相关联的一个或多个幸存者位; 和至少两个第二类型功能单元，其中每个第二类型功能单元包括多路复用器和逻辑电路，用于计算指示相应路径的位是否相等的至少一个等同位。 通常，相应的路径是失败路径和失败路径中的一个或多个。

公开(公告)号：US08205145B2

公开(公告)日：2012-06-19

申请号：US12265011

申请日：2008-11-05

申请人： Seok-Jun Lee ,  Yuming Zhu ,  Manish Goel

发明人： Seok-Jun Lee ,  Yuming Zhu ,  Manish Goel

IPC分类号： H03M13/00

CPC分类号： G06F7/22 ,  G06F7/544 ,  H03M13/395 ,  H03M13/4107

摘要： A high speed add-compare-select (ACS) circuit for a Viterbi decoder or a turbo decoder has a lower critical path delay than that achievable using a traditional ACS circuit. According to one embodiment of the invention, the path and branch metrics are split into most-significant and least-significant portions, such portions separately added in order to reduce the propagation delay.

摘要翻译： 用于维特比解码器或turbo解码器的高速加法比较选择（ACS）电路具有比使用传统ACS电路可实现的更低的关键路径延迟。 根据本发明的一个实施例，路径和分支度量被分成最重要和最不重要的部分，这些部分被分开地添加以减少传播延迟。

公开(公告)号：US08155246B2

公开(公告)日：2012-04-10

申请号：US11966833

申请日：2007-12-28

申请人： Kripa Venkatachalam ,  Brian K. Gutcher

发明人： Kripa Venkatachalam ,  Brian K. Gutcher

IPC分类号： H04L27/06

CPC分类号： H04L1/0054 ,  H03M13/395 ,  H03M13/4146 ,  H03M13/4184

摘要： Methods, apparatus, and systems for generating bit-wise path equivalency information corresponding to 1T decision nodes in a soft output Viterbi algorithm (“SOVA”) decoder operating with an nT clock signal. An add, compare, select circuit (ACS) of the SOVA generates decision data for decision nodes 1T through nT responsive to each nT clock signal pulse. The decision data is applied to corresponding 1T through nT path equivalency detector circuits to generate 1T through nT path equivalency information for generation of soft output signals corresponding to the 1T through nT decision data.

摘要翻译： 用于在用nT时钟信号操作的软输出维特比算法（“SOVA”）解码器中生成与1T判定节点相对应的逐位路径等价信息的方法，装置和系统。 SOVA的加法比较选择电路（ACS）根据每个nT时钟信号脉冲产生判决节点1T至nT的判定数据。 决定数据被应用于相应的1T到nT路径等价检测器电路，以产生1T到nT路径等价信息，用于产生对应于1T到nT判决数据的软输出信号。

公开(公告)号：US20110019781A1

公开(公告)日：2011-01-27

申请号：US12509276

申请日：2009-07-24

申请人： Guy Drory ,  Ron Bercovich ,  Aviel Livay ,  Ilia Moskovich ,  Yuval Neeman

发明人： Guy Drory ,  Ron Bercovich ,  Aviel Livay ,  Ilia Moskovich ,  Yuval Neeman

IPC分类号： H04L27/06 ,  H03M13/03

CPC分类号： H03M13/3905 ,  H03M13/2957 ,  H03M13/395 ,  H03M13/6356 ,  H03M13/6525 ,  H03M13/6558

摘要： A method for calculating backward state metrics of a trellis, the method includes: performing a radix-K calculation of backward state matrices of multiple states of at least one time instance of a trellis; and performing a radix-J calculation of backward state matrices of multiple states of at least one other time instance of the trellis; wherein K differs from J.

摘要翻译： 一种用于计算网格的后向状态度量的方法，所述方法包括：对网格的至少一个时间实例的多个状态的后向状态矩阵进行基数K计算; 以及对所述网格的至少另一个时间实例的多个状态的后向状态矩阵进行基数-J计算; 其中K与J.

公开(公告)号：US07865814B2

公开(公告)日：2011-01-04

申请号：US12547921

申请日：2009-08-26

申请人： Jonathan James Ashley ,  Kelly Knudson Fitzpatrick ,  Erich Franz Haratsch

发明人： Jonathan James Ashley ,  Kelly Knudson Fitzpatrick ,  Erich Franz Haratsch

IPC分类号： H03M13/03

CPC分类号： H03M13/4192 ,  H03M13/395 ,  H03M13/4153

摘要： A path metric difference computation unit is disclosed for computing path differences through a multiple-step trellis. Path differences are computed between paths through a multiple-step trellis, wherein a first path is a winning path for each single-step-trellis period of a multiple-step-trellis cycle, a second path is a winning path for a first single-step-trellis period and is a losing path for a second single-step-trellis period and a third path is a losing path for a first single-step-trellis period and is a winning path for a second single-step-trellis period. The disclosed path metric difference computation unit comprises path metric difference generators for generating a path metric difference Δ0 for a second single-step-trellis period based on a difference between the first path and the second path, and a path metric difference Δ−1 for a first single-step-trellis period based on a difference between the first path and the third path, wherein intermediate path metric values or intermediate path metric difference values are reused to generate the path metric differences Δ0 or Δ−1.

摘要翻译： 公开了用于通过多步网格计算路径差异的路径度量差计算单元。 在通过多步网格的路径之间计算路径差异，其中第一路径是用于多步网格周期的每个单步网格周期的获胜路径，第二路径是用于第一单步网格的获胜路径， 是阶段性格局，是第二个单步阶段的失败之路，第三个路径是第一个单步阶段的失败之路，是第二个单步阶段的获胜路径。 所公开的路径量度差计算单元包括路径度量差产生器，用于基于第一路径和第二路径之间的差异以及路径度量差Dgr，为第二单步网格周期生成路径度量差Dgr; 0; -1，用于基于第一路径和第三路径之间的差异的第一单步网格周期，其中中间路径度量值或中间路径度量差值被重用以生成路径度量差异Dgr; 0或＆Dgr; - 1。