公开(公告)号：US06972594B2

公开(公告)日：2005-12-06

申请号：US10615464

申请日：2003-07-07

申请人： Jian-Shen Yu

发明人： Jian-Shen Yu

IPC分类号： H03K3/356 ,  H03K19/0175 ,  H03K19/094

CPC分类号： H03K3/356104

摘要： A level-shifting circuit comprising an enable circuit is disclosed. The level modulating circuit includes an input terminal and an inverse input terminal for respectively receiving a complementary pair of small signals, and a first output terminal for outputting a voltage level in response to the complementary pair of small signals. The enable circuit is coupled to the first output terminal and makes the first output terminal output a predetermined voltage level signal when receiving a disable signal.

摘要翻译： 公开了一种包括使能电路的电平移动电路。 电平调制电路包括用于分别接收互补的一对小信号的输入端子和反相输入端子，以及用于响应互补的一对小信号而输出电压电平的第一输出端子。 使能电路耦合到第一输出端子，并且当接收到禁止信号时使第一输出端子输出预定的电压电平信号。

公开(公告)号：US06956552B2

公开(公告)日：2005-10-18

申请号：US10294164

申请日：2002-11-14

申请人： Jian-Shen Yu

发明人： Jian-Shen Yu

IPC分类号： G02F1/133 ,  G09G3/20 ,  G09G3/36

CPC分类号： G09G3/3677 ,  G09G3/3614 ,  G09G3/3659 ,  G09G2310/065 ,  G09G2330/021

摘要： A method for driving a display having display cells with capacitors coupled to gate lines. The method comprises the steps of floating the gates of the transistors of the Nth and (N+1)th display cell, applying a high voltage level to the gate of the transistor of the Nth display cell to turn it on and keeping the gate of the transistor of the (N+1)th display cell floated, applying a low voltage level to the gate of the transistor of the Nth display cell to turn it off and the first voltage level to the gate of the transistor of the (N+1)th display cell to turn it on, and floating the gate of the transistor of the Nth display cell and applying the low voltage level to the gate of the transistor of the (N+1)th display cell to turn it off.

摘要翻译： 一种用于驱动具有与栅极线耦合的电容器的显示单元的显示器的方法。 该方法包括以下步骤：浮置第N和第（N + 1）个显示单元的晶体管的栅极，向第N个显示单元的晶体管的栅极施加高电压电平，将其导通并保持 第（N + 1）个显示单元的晶体管浮起来，向第N个显示单元的晶体管的栅极施加低电压电平，将其截止，并将第（N + 1）个显示单元的晶体管的栅极施加第一电压电平， 1）显示单元将其导通，并且浮置第N个显示单元的晶体管的栅极并将低电压电平施加到第（N + 1）个显示单元的晶体管的栅极以使其截止。

公开(公告)号：US06894755B2

公开(公告)日：2005-05-17

申请号：US10410769

申请日：2003-04-10

申请人： Jian-Shen Yu

发明人： Jian-Shen Yu

IPC分类号： G02F1/1343 ,  G02F1/1362 ,  G09G3/30

CPC分类号： G02F1/134309 ,  G02F1/1362

摘要： A liquid crystal display (LCD) device integrating driving circuit on an active-matrix substrate. A common electrode disposed on a counter substrate has an opening slit corresponding to a clock line disposed on the matrix substrate, thereby eliminating parasitic capacitance between the clock line and the common electrode.

摘要翻译： 一种在有源矩阵基板上集成驱动电路的液晶显示器（LCD）装置。 配置在对置基板上的公共电极具有与设置在矩阵基板上的时钟线对应的开口狭缝，从而消除了时钟线与公共电极之间的寄生电容。

公开(公告)号：US20050088397A1

公开(公告)日：2005-04-28

申请号：US10708178

申请日：2004-02-13

申请人： Jian-Shen Yu ,  Shih-Chian Liu

发明人： Jian-Shen Yu ,  Shih-Chian Liu

IPC分类号： G09G3/20 ,  G09G3/36

CPC分类号： G09G3/2096 ,  G09G3/3688 ,  G09G2310/0289 ,  G09G2330/021

摘要： A clock signal amplifying method and driving stage for LCD driving circuit is provided. The driving stage includes a clock input, a level shifter, and an output buffer. Firstly, the clock input receives a cock signal oscillating between a high original level and a low original level. Thereafter, a level shifter is biased at a high target level and a low target level, and amplifies the clock signal to a relay signal, which oscillates between a high relay level and a low relay level. Lastly, the output buffer is biased at the high relay level and the low relay level for amplifying the relay signal to a target signal, which oscillates between the high target level and the low target level.

摘要翻译： 提供了用于LCD驱动电路的时钟信号放大方法和驱动级。 驱动级包括时钟输入，电平移位器和输出缓冲器。 首先，时钟输入接收在高原始电平和低原始电平之间振荡的旋转信号。 此后，电平移位器被偏置在高目标电平和低目标电平，并且将时钟信号放大到在高继电器电平和低继电器电平之间振荡的继电器信号。 最后，输出缓冲器被偏置在高继电器电平和低继电器电平，用于将继电器信号放大到目标信号，该目标信号在高目标电平和低目标电平之间振荡。

公开(公告)号：US06813331B1

公开(公告)日：2004-11-02

申请号：US10733096

申请日：2003-12-11

申请人： Jian-Shen Yu ,  Shi-Hsiang Lu ,  Chung-Hong Kuo

发明人： Jian-Shen Yu ,  Shi-Hsiang Lu ,  Chung-Hong Kuo

IPC分类号： G11C1900

CPC分类号： G11C19/28 ,  G11C19/00

摘要： A bi-directional shift-register circuit for outputting data in different turns and reducing the power loss according to a low-voltage clock signal, a first directional signal, and a second directional signal.

摘要翻译： 一种双向移位寄存器电路，用于输出不同匝数的数据，并根据低电压时钟信号，第一定向信号和第二定向信号降低功率损耗。

公开(公告)号：US06784711B2

公开(公告)日：2004-08-31

申请号：US10600785

申请日：2003-06-19

申请人： Jian-Shen Yu

发明人： Jian-Shen Yu

IPC分类号： H03K702

CPC分类号： G11C19/184 ,  G09G3/3677 ,  G09G2310/0289 ,  G09G2330/021 ,  G11C19/00 ,  G11C19/28

摘要： A sequential pulse train generator. Each stage of the sequential pulse train generator includes a dynamic shift register circuit, level shifter, and buffer composed of inverters. The dynamic shift register circuits, allow the pulse generator to operate with a low-voltage clock signal so that power consumption in transmission of the clock signal is reduced.

公开(公告)号：US06778627B2

公开(公告)日：2004-08-17

申请号：US10410951

申请日：2003-04-10

申请人： Jian-Shen Yu

发明人： Jian-Shen Yu

IPC分类号： G11C1900

CPC分类号： G11C19/00 ,  G11C19/184

摘要： A shift-register circuit. The PMOS transistor includes a first gate for receiving an inverted output signal output from a previous stage shift-register unit, a first source for receiving an output signal from the previous stage shift-register unit, and a first drain. The first NMOS transistor includes a second gate coupled to the first drain, a second drain coupled to the clock signal and a second source. The capacitor is coupled between the second gate and the second source. The second NMOS transistor includes a third gate coupled to the first source, a third drain coupled to the second source and a third source coupled to the ground level. The third NMOS transistor includes a fourth gate coupled to an output of a next stage shift-register unit, a fourth drain coupled to a connection point of the second gate and the capacitor and a fourth source coupled to the ground level. The first inverter is coupled to a connection point of the first NMOS transistor and the second NMOS transistor to output an inverted output signal. The second inverter is coupled to the first inverter to output an output signal.