公开(公告)号：US5118385A

公开(公告)日：1992-06-02

申请号：US705843

申请日：1991-05-28

Applicant: Nalin Kumar ,  Charles W. C. Lin

Inventor： Nalin Kumar ,  Charles W. C. Lin

IPC: H01L21/48 ,  H01L23/498 ,  H05K3/42 ,  H05K3/46

CPC classification number: H01L21/4857 ,  H01L23/49866 ,  H05K3/422 ,  H05K3/467 ,  H01L2924/00013 ,  H01L2924/0002

Abstract: Method for making a multilayer electrical interconnect with stacked pillars between layers using a minimal number of conventional process steps. The method includes sputtering a chromium/copper/titanium trilayer on a dielectric base, depositing a patterned mask on the trilayer, etching the exposed trilayer, removing the mask, depositing a layer of polyimide over the unetched copper, forming a via in the polyimide above the copper, electrolessly plating nickel into the via, and polishing the interconnect to form a planar top surface.

Abstract translation: 使用最少数量的常规工艺步骤在层之间制造具有堆叠柱的多层电互连的方法。 该方法包括在电介质基底上溅射铬/铜/钛三叠层，在三层上沉积图案化掩模，蚀刻暴露的三层，去除掩模，在未蚀刻的铜上沉积聚酰亚胺层，在上述聚酰亚胺中形成通孔 铜，无电镀镍到通孔中，并且研磨互连以形成平坦的顶表面。