公开(公告)号：US09553201B2

公开(公告)日：2017-01-24

申请号：US14179452

申请日：2014-02-12

Applicant: Samsung Display Co., Ltd. ,  Kobe Steel, Ltd.

Inventor： Byung Du Ahn ,  Ji Hun Lim ,  Gun Hee Kim ,  Kyoung Won Lee ,  Je Hun Lee ,  Hiroshi Goto ,  Aya Miki ,  Shinya Morita ,  Toshihiro Kugimiya ,  Yeon Hong Kim ,  Yeon Gon Mo ,  Kwang Suk Kim

IPC: H01L27/14 ,  H01L29/786

CPC classification number: H01L29/7869 ,  H01L29/78696

Abstract: The inventive concept relates to a thin film transistor and a thin film transistor array panel and, in detail, relates to a thin film transistor including an oxide semiconductor. A thin film transistor according to an exemplary embodiment of the inventive concept includes: a gate electrode; a gate insulating layer positioned on or under the gate electrode; a first semiconductor and a second semiconductor that overlap the gate electrode with the gate insulating layer interposed therebetween, the first semiconductor and the second semiconductor contacting each other; a source electrode connected to the second semiconductor; and a drain electrode connected to the second semiconductor and facing the source electrode, wherein the second semiconductor includes gallium (Ga) that is not included in the first semiconductor, and a content of gallium (Ga) in the second semiconductor is greater than 0 at. % and less than or equal to about 33 at. %.

Abstract translation: 本发明构思涉及薄膜晶体管和薄膜晶体管阵列面板，并且详细地涉及包括氧化物半导体的薄膜晶体管。 根据本发明构思的示例性实施例的薄膜晶体管包括：栅电极; 位于栅极电极上或下方的栅极绝缘层; 第一半导体和第二半导体，其与栅电极重叠，栅极绝缘层插入其间，第一半导体和第二半导体彼此接触; 连接到所述第二半导体的源电极; 和连接到第二半导体并面向源电极的漏电极，其中第二半导体包括不包括在第一半导体中的镓（Ga），并且第二半导体中的镓（Ga）的含量大于0 。 ％且小于或等于约33at。 ％。

公开(公告)号：US09508856B2

公开(公告)日：2016-11-29

申请号：US14436241

申请日：2013-10-15

Applicant: KABUSHIKI KAISHA KOBE SEIKO SHO (KOBE STEEL, LTD.) ,  Samsung Display Co., Ltd.

Inventor： Hiroaki Tao ,  Takeaki Maeda ,  Aya Miki ,  Toshihiro Kugimiya ,  Byung Du Ahn ,  So Young Koo ,  Gun Hee Kim

IPC: H01L29/786

CPC classification number: H01L29/78606 ,  H01L29/7869 ,  H01L29/78693

Abstract: Provided is a thin film transistor wherein the shape of a protrusion formed on the interface between an oxide semiconductor layer and a protection film is suitably controlled, and stable characteristics are achieved. This thin film transistor is characterized in that: the thin film transistor has an oxide semiconductor layer formed of an oxide containing at least In, Zn and Sn as metal elements, and a protection film directly in contact with the oxide semiconductor layer; and the maximum height of a protrusion formed on the oxide semiconductor layer surface directly in contact with the protection film is less than 5 nm.

Abstract translation: 提供一种薄膜晶体管，其中形成在氧化物半导体层和保护膜之间的界面上的突起的形状被适当地控制，并且实现了稳定的特性。 该薄膜晶体管的特征在于：薄膜晶体管具有由至少含有In，Zn和Sn作为金属元素的氧化物和与氧化物半导体层直接接触的保护膜形成的氧化物半导体层; 在与保护膜直接接触的氧化物半导体层表面上形成的突起的最大高度小于5nm。