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公开(公告)号：US20150249159A1
公开(公告)日：2015-09-03
申请号：US14436241
申请日：2013-10-15
发明人： Hiroaki Tao , Takeaki Maeda , Aya Miki , Toshihiro Kugimiya , Byung Du Ahn , So Young Koo , Gun Hee Kim
IPC分类号： H01L29/786
CPC分类号： H01L29/78606 , H01L29/7869 , H01L29/78693
摘要： Provided is a thin film transistor wherein the shape of a protrusion formed on the interface between an oxide semiconductor layer and a protection film is suitably controlled, and stable characteristics are achieved. This thin film transistor is characterized in that: the thin film transistor has an oxide semiconductor layer formed of an oxide containing at least In, Zn and Sn as metal elements, and a protection film directly in contact with the oxide semiconductor layer; and the maximum height of a protrusion formed on the oxide semiconductor layer surface directly in contact with the protection film is less than 5 nm.
摘要翻译： 提供一种薄膜晶体管，其中形成在氧化物半导体层和保护膜之间的界面上的突起的形状被适当地控制，并且实现了稳定的特性。 该薄膜晶体管的特征在于：薄膜晶体管具有由至少含有In，Zn和Sn作为金属元素的氧化物和与氧化物半导体层直接接触的保护膜形成的氧化物半导体层; 在与保护膜直接接触的氧化物半导体层表面上形成的突起的最大高度小于5nm。
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公开(公告)号：US20150228674A1
公开(公告)日：2015-08-13
申请号：US14423838
申请日：2013-08-30
发明人： Aya Miki , Shinya Morita , Hiroshi Goto , Hiroaki Tao , Toshihiro Kugimiya , Byung Du Ahn , Gun Hee Kim , Jin Hyun Park , Yeon Hong Kim
IPC分类号： H01L27/12 , H01L29/40 , H01L29/786
CPC分类号： H01L27/1225 , H01L21/02126 , H01L21/02164 , H01L21/0217 , H01L21/02274 , H01L29/408 , H01L29/4908 , H01L29/51 , H01L29/78606 , H01L29/7869 , H01L29/78696
摘要： Provided is a thin film transistor which is provided with an oxide semiconductor thin film layer and has a threshold voltage that does not change much due to light, a bias stress or the like, thereby exhibiting excellent stress stability. A thin film transistor of the present invention is provided with a gate electrode, an oxide semiconductor layer composed of a single layer which is used as a channel layer, an etch stopper layer to protect a surface of the oxide semiconductor layer, a source-drain electrode, and a gate insulator layer arranged between the gate electrode and the channel layer. The metal elements constituting the oxide semiconductor layer comprise In, Zn and Sn. The hydrogen concentration in the gate insulator layer in direct contact with the oxide semiconductor layer is controlled to 4 atomic % or lower.
摘要翻译： 提供一种薄膜晶体管，其设置有氧化物半导体薄膜层，并且具有由于光，偏压应力等而不会变化太大的阈值电压，从而表现出优异的应力稳定性。 本发明的薄膜晶体管设置有栅电极，由用作沟道层的单层组成的氧化物半导体层，用于保护氧化物半导体层的表面的蚀刻停止层，源极 - 漏极 电极和布置在栅电极和沟道层之间的栅极绝缘体层。 构成氧化物半导体层的金属元素包括In，Zn和Sn。 与氧化物半导体层直接接触的栅极绝缘体层中的氢浓度被控制在4原子％以下。
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公开(公告)号：US09508856B2
公开(公告)日：2016-11-29
申请号：US14436241
申请日：2013-10-15
发明人： Hiroaki Tao , Takeaki Maeda , Aya Miki , Toshihiro Kugimiya , Byung Du Ahn , So Young Koo , Gun Hee Kim
IPC分类号： H01L29/786
CPC分类号： H01L29/78606 , H01L29/7869 , H01L29/78693
摘要： Provided is a thin film transistor wherein the shape of a protrusion formed on the interface between an oxide semiconductor layer and a protection film is suitably controlled, and stable characteristics are achieved. This thin film transistor is characterized in that: the thin film transistor has an oxide semiconductor layer formed of an oxide containing at least In, Zn and Sn as metal elements, and a protection film directly in contact with the oxide semiconductor layer; and the maximum height of a protrusion formed on the oxide semiconductor layer surface directly in contact with the protection film is less than 5 nm.
摘要翻译： 提供一种薄膜晶体管，其中形成在氧化物半导体层和保护膜之间的界面上的突起的形状被适当地控制，并且实现了稳定的特性。 该薄膜晶体管的特征在于：薄膜晶体管具有由至少含有In，Zn和Sn作为金属元素的氧化物和与氧化物半导体层直接接触的保护膜形成的氧化物半导体层; 在与保护膜直接接触的氧化物半导体层表面上形成的突起的最大高度小于5nm。
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公开(公告)号：US20150206978A1
公开(公告)日：2015-07-23
申请号：US14416213
申请日：2013-08-30
发明人： Aya Miki , Shinya Morita , Hiroshi Goto , Hiroaki Tao , Toshihiro Kugimiya
IPC分类号： H01L29/786 , H01L27/12 , H01L29/51
CPC分类号： H01L27/1225 , H01L21/02126 , H01L21/02164 , H01L21/0217 , H01L21/02274 , H01L29/408 , H01L29/4908 , H01L29/51 , H01L29/78606 , H01L29/7869 , H01L29/78696
摘要： Provided is a thin film transistor comprising an oxide semiconductor thin film layer and has a threshold voltage that does not change much due to light, a bias stress or the like, thereby exhibiting excellent stress stability. A thin film transistor of the present invention is provided with: a gate electrode; two or more oxide semiconductor layers that are used as a channel layer; an etch stopper layer for protecting the surfaces of the oxide semiconductor layers; a source-drain electrode; and a gate insulator film interposed between the gate electrode and the channel layer. The metal elements constituting an oxide semiconductor layer that is in direct contact with the gate insulator film are In, Zn and Sn. The hydrogen concentration in the gate insulator film, which is in direct contact with the oxide semiconductor layer, is controlled to 4 atomic % or less.
摘要翻译： 提供了一种薄膜晶体管，其包括氧化物半导体薄膜层，并且具有由于光，偏压应力等而不会变化太大的阈值电压，从而表现出优异的应力稳定性。 本发明的薄膜晶体管设有：栅电极; 用作沟道层的两个或更多个氧化物半导体层; 用于保护氧化物半导体层的表面的蚀刻停止层; 源极 - 漏极电极; 以及插入在栅电极和沟道层之间的栅绝缘膜。 构成与栅极绝缘膜直接接触的氧化物半导体层的金属元素为In，Zn和Sn。 与氧化物半导体层直接接触的栅极绝缘膜的氢浓度被控制在4原子％以下。
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公开(公告)号：US20150171221A1
公开(公告)日：2015-06-18
申请号：US14416927
申请日：2013-08-30
发明人： Aya Miki , Shinya Morita , Hiroshi Goto , Toshihiro Kugimiya , Hiroaki Tao , Kenta Hirose
IPC分类号： H01L29/786
摘要： Provided is a thin film transistor comprising an oxide semiconductor thin film layer and has a threshold voltage that does not change much due to light, a bias stress or the like, thereby exhibiting excellent stress stability. A thin film transistor of the present invention is provided with: a gate electrode; an oxide semiconductor layer that is used as a channel layer; and a gate insulator film that is arranged between the gate electrode and the channel layer. The oxide semiconductor layer is configured of at least one metal element that is selected from the group consisting of In, Ga, Zn and Sn (excluding the cases where the oxide semiconductor layer is constituted of metal elements Sn, and at least one of In and Zn). The hydrogen concentration in the gate insulator film, which is in direct contact with the oxide semiconductor layer, is controlled to 4 atomic % or less.
摘要翻译： 提供了一种薄膜晶体管，其包括氧化物半导体薄膜层，并且具有由于光，偏压应力等而不会变化太大的阈值电压，从而表现出优异的应力稳定性。 本发明的薄膜晶体管设有：栅电极; 用作沟道层的氧化物半导体层; 以及布置在栅电极和沟道层之间的栅极绝缘膜。 氧化物半导体层由选自In，Ga，Zn和Sn中的至少一种金属元素构成（除了氧化物半导体层由金属元素Sn构成的情况以及In和 Zn）。 与氧化物半导体层直接接触的栅极绝缘膜的氢浓度被控制在4原子％以下。
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6.发明申请OXIDE FOR SEMICONDUCTOR LAYER IN THIN FILM TRANSISTOR, THIN FILM TRANSISTOR, DISPLAY DEVICE, AND SPUTTERING TARGET 有权薄膜晶体管，薄膜晶体管，显示器件和溅射靶的半导体层氧化物公开(公告)号：US20150076489A1
公开(公告)日：2015-03-19
申请号：US14394530
申请日：2013-05-28
发明人： Shinya Morita , Kenta Hirose , Aya Miki , Toshihiro Kugimiya
IPC分类号： H01L29/786 , H01J37/34
CPC分类号： H01L29/7869 , C23C14/08 , C23C14/3414 , H01J37/3429 , H01J2237/332 , H01L21/02554 , H01L21/02565
摘要： Provided is an oxide semiconductor configured to be used in a thin film transistor having high field-effect mobility; a small shift in threshold voltages against light and bias stress; excellent stress resistance. The oxide semiconductor has also excellent resistance to a wet-etchant for patterning of a source-drain electrode. The oxide semiconductor comprises In, Zn, Ga, Sn and O, and satisfies the requirements represented by expressions (1) to (4) shown below, wherein [In], [Zn], [Ga], and [Sn] represent content (in atomic %) of each of the elements relative to the total content of all the metal elements other than oxygen in the oxide. (1.67×[Zn]+1.67×[Ga])≧100 (1) {([Zn]/0.95)+([Sn]/0.40)+([In]/0.4)}≧100 (2) [In]≦40 (3) [Sn]≧5 (4)
摘要翻译： 提供一种构造成用于具有高场效应迁移率的薄膜晶体管的氧化物半导体; 阈值电压对光和偏置应力的微小偏移; 优异的抗压性。 氧化物半导体对于用于图案化源极 - 漏极电极的湿蚀刻剂也具有优异的抗性。 氧化物半导体包含In，Zn，Ga，Sn和O，满足下述式（1）〜（4）所示的要求，[In]，[Zn]，[Ga]，[Sn] （原子％）相对于除了氧化物中的氧以外的所有金属元素的总含量。 （1.67×[Zn] + 1.67×[Ga]）≥100（1）{（[Zn] /0.95）+（[Sn] /0.40）+（[In] /0.4）}≥100（2） ]＆nlE; 40（3）[Sn]≥5（4）
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公开(公告)号：US20150123116A1
公开(公告)日：2015-05-07
申请号：US14399378
申请日：2013-06-06
发明人： Hiroshi Goto , Aya Miki , Tomoya Kishi , Kenta Hirose , Shinya Morita , Toshihiro Kugimiya
IPC分类号： H01L29/786 , H01L29/24
CPC分类号： H01L29/78693 , C23C14/08 , H01L21/02554 , H01L21/02565 , H01L21/02631 , H01L27/1225 , H01L29/24 , H01L29/78606 , H01L29/78696
摘要： Provided is a thin film transistor having an oxide semiconductor layer that has high mobility, excellent stress resistance, and good wet etching property. The thin film transistor comprises at least, a gate electrode, a gate insulating film, an oxide semiconductor layer, source-drain electrode and a passivation film, in this order on a substrate. The oxide semiconductor layer is a laminate comprising a first oxide semiconductor layer (IGZTO) and a second oxide semiconductor layer (IZTO). The second oxide semiconductor layer is formed on the gate insulating film, and the first oxide semiconductor layer is formed between the second oxide semiconductor layer and the passivation film. The contents of respective metal elements relative to the total amount of all the metal elements other than oxygen in the first oxide semiconductor layer are as follows; Ga: 5% or more; In: 25% or less (excluding 0%); Zn: 35 to 65%; and Sn: 8 to 30%.
摘要翻译： 提供了具有高迁移率，优异的耐应力和良好的湿蚀刻性能的氧化物半导体层的薄膜晶体管。 薄膜晶体管至少包括栅电极，栅极绝缘膜，氧化物半导体层，源 - 漏电极和钝化膜。 氧化物半导体层是包括第一氧化物半导体层（IGZTO）和第二氧化物半导体层（IZTO）的层压体。 第二氧化物半导体层形成在栅极绝缘膜上，第一氧化物半导体层形成在第二氧化物半导体层和钝化膜之间。 各金属元素相对于第一氧化物半导体层中除氧以外的全部金属元素的总量的含量如下： Ga：5％以上; 在：25％以下（不包括0％）; Zn：35〜65％ 和Sn：8〜30％。
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8.发明申请CU ALLOY INTERCONNECTION FILM FOR TOUCH-PANEL SENSOR AND METHOD OF MANUFACTURING THE INTERCONNECTION FILM, TOUCH-PANEL SENSOR, AND SPUTTERING TARGET 审中-公开用于触摸屏传感器的CU合金互连膜和制造互连膜，触摸屏传感器和溅射目标的方法公开(公告)号：US20130140066A1
公开(公告)日：2013-06-06
申请号：US13661902
申请日：2012-10-26
发明人： Hiroyuki Okuno , Aya Miki , Toshihiro Kugimiya
CPC分类号： C22C9/00 , B22F3/10 , C22C9/04 , C22C9/05 , C22C9/06 , C22C2204/00 , C23C14/185 , C23C14/3414 , H01B1/026
摘要： Provided is a Cu alloy interconnection film for touch-panel sensors, which excels in oxidation resistance and adhesion properties, and is low in electrical resistance. The interconnection film contains at least one alloy element selected from a group consisting of Ni, Zn, and Mn by 0.1 to 40 atom % in total, and the remainder contains Cu and inevitable impurities. Alternatively, the interconnection film is made of a Cu alloy containing at least one element selected from the group consisting of Ni, Zn, and Mn. In this case, if the Cu alloy contains one element, Ni is contained by 0.1 to 6 atom %, or Zn is contained by 0.1 to 6 atom %, or Mn is contained by 0.1 to 1.9 atom %. On the other hand, if two or more alloy elements are contained, the alloy elements are contained by 0.1 to 6 atom % in total (wherein, Mn is contained by [((6−x)×2)/6] atom % or less if Mn is contained; here, x is a total adding amount of Ni and Zn).
摘要翻译： 提供一种用于触摸面板传感器的Cu合金互连膜，其耐氧化性和粘附性优异，并且电阻低。 互连膜含有选自Ni，Zn和Mn中的至少一种合金元素，总计为0.1至40原子％，余量包含Cu和不可避免的杂质。 或者，互连膜由含有选自Ni，Zn和Mn中的至少一种元素的Cu合金制成。 在这种情况下，如果Cu合金含有一种元素，则Ni的含量为0.1〜6原子％，或含有0.1〜6原子％的Zn，或含有0.1〜1.9原子％的Mn。 另一方面，如果含有两种以上的合金元素，则合金元素总计含有0.1〜6原子％（其中，Mn含有[（（6-x）×2）/ 6]原子％或 如果含有Mn，则少;这里，x是Ni和Zn的总添加量）。
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公开(公告)号：US10566457B2
公开(公告)日：2020-02-18
申请号：US14416927
申请日：2013-08-30
发明人： Aya Miki , Shinya Morita , Hiroshi Goto , Toshihiro Kugimiya , Hiroaki Tao , Kenta Hirose
IPC分类号： H01L29/786 , H01L21/8234
摘要： Provided is a thin film transistor comprising an oxide semiconductor thin film layer and has a threshold voltage that does not change much due to light, a bias stress or the like, thereby exhibiting excellent stress stability. A thin film transistor of the present invention is provided with: a gate electrode; an oxide semiconductor layer that is used as a channel layer; and a gate insulator film that is arranged between the gate electrode and the channel layer. The oxide semiconductor layer is configured of at least one metal element that is selected from the group consisting of In, Ga, Zn and Sn (excluding the cases where the oxide semiconductor layer is constituted of metal elements Sn, and at least one of In and Zn). The hydrogen concentration in the gate insulator film, which is in direct contact with the oxide semiconductor layer, is controlled to 4 atomic % or less.
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公开(公告)号：US20150091000A1
公开(公告)日：2015-04-02
申请号：US14387496
申请日：2013-05-08
发明人： Shinya Morita , Aya Miki , Hiroaki Tao , Toshihiro Kugimiya
IPC分类号： H01L27/12 , H01L29/786
CPC分类号： H01L27/1225 , H01L29/78606 , H01L29/7869 , H01L29/78693 , H01L29/78696
摘要： Provided is an oxide-semiconductor-based thin film transistor having satisfactory switching characteristics and stress resistance. Change in threshold voltage through stress application is suppressed in the thin film transistor. The thin film transistor of excellent stability comprises a substrate and, formed thereon, at least a gate electrode, a gate insulating film, oxide semiconductor layers, a source-drain electrode, and a passivation film for protecting the gate insulating film, and oxide semiconductor layers, wherein the oxide semiconductor layers are laminated layers comprising a second oxide semiconductor layer consisting of In, Zn, Sn, and O and a first oxide semiconductor layer consisting of In, Ga, Zn, and O. The second oxide semiconductor layer is formed on the gate insulating film. The first oxide semiconductor layer is interposed between the second oxide semiconductor layer and the passivation film.
摘要翻译： 提供了具有令人满意的开关特性和耐应力的氧化物半导体薄膜晶体管。 在薄膜晶体管中抑制了通过应力施加的阈值电压的变化。 具有优异稳定性的薄膜晶体管包括基板，并且在其上形成至少栅电极，栅极绝缘膜，氧化物半导体层，源 - 漏电极和用于保护栅极绝缘膜的钝化膜，以及氧化物半导体 层，其中氧化物半导体层是包括由In，Zn，Sn和O组成的第二氧化物半导体层和由In，Ga，Zn和O组成的第一氧化物半导体层的层叠层。形成第二氧化物半导体层 在栅极绝缘膜上。 第一氧化物半导体层介于第二氧化物半导体层和钝化膜之间。
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