公开(公告)号：US20160210926A1

公开(公告)日：2016-07-21

申请号：US14862388

申请日：2015-09-23

Applicant: Samsung Display Co., Ltd.

Inventor： Tadashi AMINO ,  Jong Hee KIM ,  Masataka KANO ,  Jun Hyun PARK

IPC: G09G3/36 ,  H01L27/12

CPC classification number: G09G3/3677 ,  G09G2300/0408 ,  G09G2300/0417 ,  G11C19/184 ,  G11C19/28 ,  H01L27/124 ,  H01L27/1255

Abstract: A Rate driving circuit including: a plurality of stages outputting signals to gate lines, the stages includes a first transistor of which one end and a control terminal are connected, one end and the control terminal are connected with a first input terminal, and the other end is connected to a second node, a second transistor including a control terminal connected to a first node, connected with a clock input terminal, and the other end connected to a first output terminal, a first capacitor of which one end is connected to the first node, the other end is connected to the other end of the second transistor and the first output terminal, and a third transistor of which one end is connected to the other end of the first transistor, the other end is connected with the first node, and a control terminal is connected to a third node.

Abstract translation: A速率驱动电路包括：多个阶段向栅线输出信号，该级包括一端和控制端连接的第一晶体管，一端与控制端与第一输入端连接，另一端 端部连接到第二节点，第二晶体管包括连接到与时钟输入端子连接的第一节点的控制端子，以及连接到第一输出端子的另一端，其一端连接到第一节点的第一电容器 第一节点，另一端连接到第二晶体管和第一输出端子的另一端，第三晶体管的一端连接到第一晶体管的另一端，另一端与第一节点连接 并且控制终端连接到第三节点。