Abstract:
An emission driver is disclosed that includes stages. Each of the stages includes a first circuit part configured to apply a first node voltage to a first node, a second circuit part configured to apply a second node voltage to a second node and connected to the first circuit part through a third node, a third circuit part configured to apply a third node voltage of the third node or a voltage higher than the third node voltage to a fourth node based on the first node voltage and the second node voltage, and a fourth circuit part configured to generate an emission signal based on the first node voltage and a fourth node voltage of the fourth node.
Abstract:
A display device includes a scan driver to supply scan signals to first and second scan lines, a data driver to supply a data signal to data lines, a sensor connected to sensing lines, and pixels including a light-emitting element, a driving transistor to control an amount of current supplied to the light-emitting element in response to a voltage of a first node, a switching transistor between a j-th data line and the first node, and including a gate electrode coupled to an i-th first scan line, and a sensing transistor coupled between a second node, which is between the light-emitting element and the driving transistor, and a k-th sensing line, and including a gate electrode coupled to an i-th second scan line, and wherein the sensor is to sense deterioration information of the light-emitting element in a state in which the switching and sensing transistors are turned on.
Abstract:
A scan driver includes scan stages, an n-th scan stage of the scan stages includes a first driving circuit, a second driving circuit, and an output circuit. The first driving circuit controls a voltage of a first driving node, based on an input signal and a voltage of a second driving node. The second driving circuit controls the voltage of the second driving node, based on a second clock signal and a first voltage. The output circuit outputs a first clock signal as a scan signal and a carry signal, and outputs a second voltage as the scan signal and the carry signal. The first driving circuit includes a first transistor including a gate electrode electrically connected to the second driving node, one electrode electrically connected to an input line that provides the input signal, and another electrode electrically connected to the first driving node.
Abstract:
A display device includes a gate driver for applying scan signals and including a plurality of gate driving circuit blocks, and a data driver for applying a data voltage to data lines, wherein the gate driving circuit blocks respectively output a carry signal to be transmitted to a first input terminal of a subsequent gate driving circuit block based on a signal applied to a first control node through a first input terminal and a carry clock signal input to a carry clock input terminal, output a scan signal to a first scan line based on the signal applied to the first control node and a scan clock signal input to a first scan clock input terminal, and output a scan signal to a second scan line based on the signal applied to the first control node and a scan clock signal input to a second scan clock input terminal.
Abstract:
A gate circuit according to an exemplary embodiment of the present inventive concept comprises a plurality of stages, each receiving a clock signal and outputting a gate signal and a carry signal. One of the plurality of stages includes a first transistor of which a first terminal and a control terminal are connected to each other and a carry signal of a stage before previous stage is input to the first terminal and the control terminal and a second transistor of which a gate signal of the previous stage is input to a first terminal, a control terminal is connected with a second terminal of the first transistor, and an output terminal is connected to a first node.
Abstract:
A Rate driving circuit including: a plurality of stages outputting signals to gate lines, the stages includes a first transistor of which one end and a control terminal are connected, one end and the control terminal are connected with a first input terminal, and the other end is connected to a second node, a second transistor including a control terminal connected to a first node, connected with a clock input terminal, and the other end connected to a first output terminal, a first capacitor of which one end is connected to the first node, the other end is connected to the other end of the second transistor and the first output terminal, and a third transistor of which one end is connected to the other end of the first transistor, the other end is connected with the first node, and a control terminal is connected to a third node.
Abstract:
A scan driver for a display device may include a plurality of scan stage groups, each of the scan stage groups including a first scan stage and a second scan stage. The first scan stage may include: a first transistor including a gate electrode coupled to a first Q node, one electrode coupled to a first scan clock line, and another electrode coupled to a first scan line; a second transistor including a gate electrode and one electrode, which are coupled to a first scan carry line, and another electrode coupled to the first Q node; a third transistor including a gate electrode coupled to a first control line and one electrode coupled to a first sensing carry line; a fourth transistor including a gate electrode coupled to the other electrode of the third transistor, one electrode coupled to a second control line, and another electrode coupled to a first node; a first capacitor including one electrode coupled to the one electrode of the fourth transistor and another electrode coupled to the gate electrode of the fourth transistor; a fifth transistor including a gate electrode coupled to a third control line, one electrode coupled to the first node, and another electrode coupled to the first Q node; and a sixth transistor including a gate electrode coupled to the first Q node, one electrode coupled to the second control line, and another electrode coupled to the first node.
Abstract:
A stage includes a first transistor including an input terminal to which a clock signal is applied and a control terminal connected to a first node; a first capacitor including terminals respectively connected to the first node and an output terminal of the first transistor; a second transistor including an input terminal connected to the output terminal of the first transistor, a control terminal connected to a second node, and an output terminal to which a low voltage is applied; a third transistor including an output terminal connected to the second node, a control terminal connected to the first node, and an input terminal to which the low voltage is applied; and a fourth transistor including an input terminal connected to the first node and an output terminal to which the low voltage is applied, wherein the fourth transistor is switched according to an output signal of a next stage.
Abstract:
A display device includes a display panel including a gate line, a data line, and a pixel connected to the gate line and the data line, a data driver connected to the data line, a gate driver connected to the gate line, and a signal controller controlling the data driver and the gate driver, wherein a circuits powering power source voltage that is normally used for driving the data driver is selectively not applied during a new-image blanking time when the signal controller is not supplying image data to the data driver.
Abstract:
A scan driver includes scan stages, an n-th scan stage of the scan stages includes a first driving circuit, a second driving circuit, and an output circuit. The first driving circuit controls a voltage of a first driving node, based on an input signal and a voltage of a second driving node. The second driving circuit controls the voltage of the second driving node, based on a second clock signal and a first voltage. The output circuit outputs a first clock signal as a scan signal and a carry signal, and outputs a second voltage as the scan signal and the carry signal. The first driving circuit includes a first transistor including a gate electrode electrically connected to the second driving node, one electrode electrically connected to an input line that provides the input signal, and another electrode electrically connected to the first driving node.