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公开(公告)号：US20200302217A1
公开(公告)日：2020-09-24
申请号：US16898972
申请日：2020-06-11
Applicant: Texas Instruments Incorporated
Inventor： Mihir Narendra Mody , Manu Mathew , Chaitanya Satish Ghone
Abstract: A method for analyzing images to generate a plurality of output features includes receiving input features of the image and performing Fourier transforms on each input feature. Kernels having coefficients of a plurality of trained features are received and on-the-fly Fourier transforms (OTF-FTs) are performed on the coefficients in the kernels. The output of each Fourier transform and each OTF-FT are multiplied together to generate a plurality of products and each of the products are added to produce one sum for each output feature. Two-dimensional inverse Fourier transforms are performed on each sum.
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72.发明申请公开(公告)号：US20200294300A1
公开(公告)日：2020-09-17
申请号：US16353792
申请日：2019-03-14
Applicant: Texas Instruments Incorporated
Inventor： Mihir Narendra Mody , Ajay Jayaraj , Hemant Hariyani , Anand Balagopalakrishnan , Jason A.T. Jones , Erick Zadiel Narvaez
Abstract: Methods, apparatus, systems and articles of manufacture to perform graphics processing on combinations of graphic processing units and digital signal processors are disclosed. A disclosed example method includes processing first data representing input vertices to create second data, the first data using a first format organized by vertex, the second data using a second format organized by components of the vertices. A digital signal processor (DSP) is to perform vertex shading on the second data to create third data, the third data formatted using the second format, the vertex shading performed by executing a first instruction at the DSP, the first instruction generated based on a second instruction capable of being executed at a graphics processing unit (GPU). The third data is processed to create fourth data, the fourth data formatted using the first format.
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公开(公告)号：US10776167B2
公开(公告)日：2020-09-15
申请号：US15269952
申请日：2016-09-19
Applicant: Texas Instruments Incorporated
Inventor： Niraj Nandan , Hetul Sanghvi , Mihir Narendra Mody
Abstract: A hardware thread scheduler (HTS) is provided for a multiprocessor system. The HTS is configured to schedule processing of multiple threads of execution by resolving data dependencies between producer modules and consumer modules for each thread. Pattern adaptors may be provided in the scheduler that allows mixing of multiple data patterns across blocks of data. Transaction aggregators may be provided that allow re-using the same image data by multiple threads of execution while the image date remains in a given data buffer. Bandwidth control may be provided using programmable delays on initiation of thread execution. Failure and hang detection may be provided using multiple watchdog timers.
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公开(公告)号：US10713522B2
公开(公告)日：2020-07-14
申请号：US16400149
申请日：2019-05-01
Applicant: Texas Instruments Incorporated
Inventor： Mihir Narendra Mody , Manu Mathew , Chaitanya Satish Ghone
Abstract: A method for analyzing images to generate a plurality of output features includes receiving input features of the image and performing Fourier transforms on each input feature. Kernels having coefficients of a plurality of trained features are received and on-the-fly Fourier transforms (OTF-FTs) are performed on the coefficients in the kernels. The output of each Fourier transform and each OTF-FT are multiplied together to generate a plurality of products and each of the products are added to produce one sum for each output feature. Two-dimensional inverse Fourier transforms are performed on each sum.
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公开(公告)号：US20190286483A1
公开(公告)日：2019-09-19
申请号：US16298709
申请日：2019-03-11
Applicant: Texas Instruments Incorporated
Inventor： Kedar Chitnis , Mihir Narendra Mody , Jesse Gregory Villarreal, JR. , Lucas Carl Weaver , Brijesh Jadav , Niraj Nandan
Abstract: Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to implement thread scheduling for multithreaded data processing environments are disclosed. Example thread schedulers disclosed herein for a data processing system include a buffer manager to determine availability of respective buffers to be acquired for respective processing threads implementing respective functional nodes of a processing flow, and to identify first ones of the processing threads as stalled due to unavailability of at least one buffer in the respective buffers to be acquired for the first ones of the processing threads. Disclosed example thread schedulers also include a thread execution manager to initiate execution of second ones of the processing threads that are not identified as stalled.
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Patent Agency Ranking
公开(公告)号：US20190258891A1
公开(公告)日：2019-08-22
申请号：US16400149
申请日：2019-05-01
Applicant: Texas Instruments Incorporated
Inventor： Mihir Narendra Mody , Manu Mathew , Chaitanya Satish Ghone
Abstract: A method for analyzing images to generate a plurality of output features includes receiving input features of the image and performing Fourier transforms on each input feature. Kernels having coefficients of a plurality of trained features are received and on-the-fly Fourier transforms (OTF-FTs) are performed on the coefficients in the kernels. The output of each Fourier transform and each OTF-FT are multiplied together to generate a plurality of products and each of the products are added to produce one sum for each output feature. Two-dimensional inverse Fourier transforms are performed on each sum.
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77.发明申请公开(公告)号：US20190188066A1
公开(公告)日：2019-06-20
申请号：US15844170
申请日：2017-12-15
Applicant: Texas Instruments Incorporated
Inventor： Mihir Narendra Mody , Niraj Nandan , Hetul Sanghvi , Manoj Koul
CPC classification number: G06F11/079 , G06F11/0736 , G06F11/0751 , G06F11/0772 , G06K9/6202 , G06T5/00 , G06T7/0002 , H04L41/0677
Abstract: Methods, apparatus, and articles of manufacture providing an efficient safety mechanism for signal processing hardware are disclosed. An example apparatus includes an input interface to receive an input signal; a hardware accelerator to process the input signal, the hardware accelerator including: unprotected memory to store non-critical data corresponding to the input signal; and protected memory to store critical data corresponding to the input signal; and an output interface to transmit the processed input signal.
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公开(公告)号：US10325173B2
公开(公告)日：2019-06-18
申请号：US16108237
申请日：2018-08-22
Applicant: Texas Instruments Incorporated
Inventor： Mihir Narendra Mody , Manu Mathew , Chaitanya Satish Ghone
Abstract: A method for analyzing images to generate a plurality of output features includes receiving input features of the image and performing Fourier transforms on each input feature. Kernels having coefficients of a plurality of trained features are received and on-the-fly Fourier transforms (OTF-FTs) are performed on the coefficients in the kernels. The output of each Fourier transform and each OTF-FT are multiplied together to generate a plurality of products and each of the products are added to produce one sum for each output feature. Two-dimensional inverse Fourier transforms are performed on each sum.
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公开(公告)号：US20190130534A1
公开(公告)日：2019-05-02
申请号：US16178200
申请日：2018-11-01
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Mihir Narendra Mody , Shashank Dabral , Jesse Gregory Villarreal , William Wallace , Niraj Nandan
Abstract: A method for filtering noise for imaging includes receiving an image frame having position and range data. A filter size divides the frame into filter windows for processing each of the filter windows. For the first pixel, a space to the center pixel and a range difference between this pixel and the center pixel is determined and used for choosing a selected weight from weights in a 2D weight LUT including weighting for space and range difference, a filtered range value is calculated by applying the selected 2D weight to the pixel, and the range, filtered range value and selected 2D weight are summed. The determining, choosing, calculating and summing are repeated for at least the second pixel. A total sum of contributions from the first and second pixel are divided by the sum of selected 2D weights to generate a final filtered range value for the center pixel.
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公开(公告)号：US09706229B2
公开(公告)日：2017-07-11
申请号：US13950042
申请日：2013-07-24
Applicant: Texas Instruments Incorporated
Inventor： Mihir Narendra Mody , Chaitanya S Ghone , Joseph Meehan
Abstract: A VP8 video decoder is implemented by partitioning the required functions across multiple sub systems, with an optimal mapping to existing functional blocks. Key optimizations include the reuse of hardware designed for prior generation V^6 and VP7 decoders. In order to reduce implementation complexity, cost and power consumption, a non exact, approximate deblocking loop filter is implemented.
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