公开(公告)号：US11202102B2

公开(公告)日：2021-12-14

申请号：US16838132

申请日：2020-04-02

Applicant: Texas Instruments Incorporated

Inventor： Niraj Nandan ,  Mullangi Venkata Ratna Reddy

IPC: H04N19/80 ,  H04N19/423 ,  H04N19/86

Abstract: A de-blocking filter includes a reconstructed memory that is configured to store reconstructed pixels corresponding to a current macroblock of a video image to be filtered. The current macroblock includes a set of sub-blocks, each sub-block having horizontal edges and vertical edges. An internal pixel buffer in the de-blocking filter is configured to store pixels corresponding to the set of sub-blocks from the reconstructed memory, and to store partially filtered pixels corresponding to a set of partially filtered macroblocks. An edge order controller in the de-blocking filter is configured to load the pixels corresponding to the set of sub-blocks into a filter engine from the internal pixel buffer, to filter the set of sub-blocks, such that, at least one horizontal edge is filtered before filtering all vertical edges of the set of sub-blocks.

公开(公告)号：US20210326229A1

公开(公告)日：2021-10-21

申请号：US17135481

申请日：2020-12-28

Applicant: Texas Instruments Incorporated

Inventor： Rajat Sagar ,  Niraj Nandan ,  Kedar Chitnis ,  Brijesh Jadav ,  Mihir Mody

IPC: G06F11/30 ,  G06F11/07 ,  G06F15/78

Abstract: Methods, apparatus, systems and articles of manufacture for an example event processor are disclosed to retrieve an input event and an input event timestamp corresponding to the input event, generate an output event based on the input event and the input event timestamp, in response to determination that an input event threshold is exceeded within a threshold of time, and an anomaly detector to retrieve the output event, determine whether the output event indicates threat to functional safety of a system on a chip, and in response to determining the output event indicates threat to functional safety of the system on a chip, adapt a process for the system on a chip to preserve functional safety.

公开(公告)号：US20210209041A1

公开(公告)日：2021-07-08

申请号：US17139970

申请日：2020-12-31

Applicant: Texas Instruments Incorporated

Inventor： Niraj Nandan ,  Rajasekhar Reddy Allu ,  Brian Chae ,  Mihir Mody

IPC: G06F13/28 ,  G06F9/48 ,  G06F13/40 ,  G06F13/16

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed herein to enable data aggregation and pattern adaptation in hardware acceleration subsystems. In some examples, a hardware acceleration subsystem includes a first scheduler, a first hardware accelerator coupled to the first scheduler to process at least a first data element and a second data element, and a first load store engine coupled to the first hardware accelerator, the first load store engine configured to communicate with the first scheduler at a superblock level by sending a done signal to the first scheduler in response to determining that a block count is equal to a first BPR value and aggregate the first data element and the second data element based on the first BPR value to generate a first aggregated data element.

公开(公告)号：US20210055970A1

公开(公告)日：2021-02-25

申请号：US17012223

申请日：2020-09-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Niraj Nandan ,  Hetul Sanghvi ,  Mihir Narendra Mody

IPC: G06F9/50 ,  G06F9/48 ,  G06F11/07 ,  G06F9/52

Abstract: A hardware thread scheduler (HTS) is provided for a multiprocessor system. The HTS is configured to schedule processing of multiple threads of execution by resolving data dependencies between producer modules and consumer modules for each thread. Pattern adaptors may be provided in the scheduler that allows mixing of multiple data patterns across blocks of data. Transaction aggregators may be provided that allow re-using the same image data by multiple threads of execution while the image data remains in a given data buffer. Bandwidth control may be provided using programmable delays on initiation of thread execution. Failure and hang detection may be provided using multiple watchdog timers.

公开(公告)号：US10467765B2

公开(公告)日：2019-11-05

申请号：US15638123

申请日：2017-06-29

Applicant: Texas Instruments Incorporated

Inventor： Hetul Sanghvi ,  Mihir Narendra Mody ,  Niraj Nandan ,  Anish Reghunath ,  Michael Peter Lachmayr

IPC: G06T7/20 ,  G06T7/246 ,  G06T7/269

Abstract: A computer vision system is provided that includes an image generation device configured to generate consecutive two dimensional (2D) images of a scene, and a dense optical flow engine (DOFE) configured to determine a dense optical flow map for pairs of the consecutive 2D images, wherein, for a pair of consecutive 2D images, the DOFE is configured to perform a predictor based correspondence search for each paxel in a current image of the pair of consecutive 2D images, wherein, for an anchor pixel in each paxel, the predictor based correspondence search evaluates a plurality of predictors to select a best matching pixel in a reference image of the pair of consecutive 2D images, and determine optical flow vectors for each pixel in a paxel based on the best matching pixel selected for the anchor pixel of the paxel.

公开(公告)号：US10397591B2

公开(公告)日：2019-08-27

申请号：US14684334

申请日：2015-04-11

Applicant: Texas Instruments Incorporated

Inventor： Dipan Kumar Mandal ,  Mihir Narendra Mody ,  Mahesh Madhukar Mehendale ,  Chaitanya Satish Ghone ,  Piyali Goswami ,  Naresh Kumar Yadav ,  Hetul Sanghvi ,  Niraj Nandan

IPC: H04N19/43 ,  H04N19/42 ,  H04N19/463 ,  G06F9/38

Abstract: A control processor for a video encode-decode engine is provided that includes an instruction pipeline. The instruction pipeline includes an instruction fetch stage coupled to an instruction memory to fetch instructions, an instruction decoding stage coupled to the instruction fetch stage to receive the fetched instructions, and an execution stage coupled to the instruction decoding stage to receive and execute decoded instructions. The instruction decoding stage and the instruction execution stage are configured to decode and execute a set of instructions in an instruction set of the control processor that are designed specifically for accelerating video sequence encoding and encoded video bit stream decoding.

公开(公告)号：US20190005335A1

公开(公告)日：2019-01-03

申请号：US15638142

申请日：2017-06-29

Applicant: Texas Instruments Incorporated

Inventor： Hetul Sanghvi ,  Mihir Narendra Mody ,  Niraj Nandan ,  Anish Reghunath ,  Michael Peter Lachmayr

IPC: G06K9/00 ,  G06T7/20 ,  G06T1/00

Abstract: A computer vision system is provided that includes an image generation device configured to capture consecutive two dimensional (2D) images of a scene, a first memory configured to store the consecutive 2D images, a second memory configured to store a growing window of consecutive rows of a reference image and a growing window of consecutive rows of a current image, wherein the reference image and the current image are a pair of consecutive 2D images stored in the first memory, a third memory configured to store a sliding window of pixels fetched from the growing window of the reference image, wherein the pixels in the sliding window are stored in tiles, and a dense optical flow engine (DOFE) configured to determine a dense optical flow map for the pair of consecutive 2D images, wherein the DOFE uses the sliding window as a search window for pixel correspondence searches.

公开(公告)号：US20180192060A1

公开(公告)日：2018-07-05

申请号：US15853474

申请日：2017-12-22

Applicant: Texas Instruments Incorporated

Inventor： Mihir Narendra Mody ,  Niraj Nandan ,  Hideo Tamama

IPC: H04N19/176 ,  H04N19/117 ,  H04N19/86

CPC classification number: H04N19/176 ,  H04N19/117 ,  H04N19/14 ,  H04N19/186 ,  H04N19/82 ,  H04N19/86

Abstract: A method of de-blocking filtering a processed video is provided. The processed video includes a plurality of blocks and each block includes a plurality of sub-blocks. A current block of the plurality of blocks includes vertical edges and horizontal edges. The processed video further includes a set of control parameters and reconstructed pixels corresponding to the current block. A boundary strength index is estimated at the vertical edges and at the horizontal edges of the current block. The set of control parameters, the reconstructed pixels corresponding to the current block and partially filtered pixels corresponding to a set of adjacent sub-blocks are loaded. The vertical edges and the horizontal edges of the current block are filtered based on the boundary strength index and the set of control parameters such that a vertical edge of the current block is filtered before filtering at least one horizontal edge of the current block.

公开(公告)号：US20180189105A1

公开(公告)日：2018-07-05

申请号：US15396153

申请日：2016-12-30

Applicant: Texas Instruments Incorporated

Inventor： Hetul Sanghvi ,  Niraj Nandan ,  Mihir Narendra Mody ,  Kedar Satish Chitnis

IPC: G06F9/50 ,  G06F9/46

CPC classification number: G06F9/5027 ,  G06F9/4812 ,  G06F2209/5018

Abstract: A data processing device is provided that includes a plurality of hardware data processing nodes, wherein each hardware data processing node is configured to execute a task, and a hardware thread scheduler coupled to the plurality of hardware data processing nodes, the hardware thread scheduler configurable to concurrently execute a first thread of tasks and a second thread of tasks on the plurality of hardware data processing nodes.

公开(公告)号：US20180189102A1

公开(公告)日：2018-07-05

申请号：US15396172

申请日：2016-12-30

Applicant: Texas Instruments Incorporated

Inventor： Hetul Sanghvi ,  Niraj Nandan ,  Mihir Narendra Mody ,  Kedar Satish Chitnis

IPC: G06F9/48

CPC classification number: G06F9/4812 ,  G06F9/5027 ,  G06F2209/5018

Abstract: A data processing device is provided that includes a plurality of hardware data processing nodes, wherein each hardware data processing node performs a task, and a hardware thread scheduler including a plurality of hardware task schedulers configured to control execution of a respective task on a respective hardware data processing node of the plurality of hardware data processing nodes, and a proxy hardware task scheduler coupled to a data processing node external to the data processing device, wherein the proxy hardware task scheduler is configured to control execution of a task by the external data processing device, wherein the hardware thread scheduler is configurable to execute a thread of tasks, the tasks including the task controlled by the proxy hardware task scheduler and a first task controlled by a first hardware task scheduler of the plurality of hardware task schedulers.