公开(公告)号：US4924459A

公开(公告)日：1990-05-08

申请号：US250026

申请日：1988-09-27

申请人： Eric H. Angell ,  Thomas J. Aprille ,  Rong-Chin Fang ,  Byeong G. Lee ,  Jan-Dieter Spalink

发明人： Eric H. Angell ,  Thomas J. Aprille ,  Rong-Chin Fang ,  Byeong G. Lee ,  Jan-Dieter Spalink

IPC分类号： H04J3/16

CPC分类号： H04J3/1641

摘要： A plurality of digital signals of one or more digital transmission bit rates are combined into a single transmission signal by employing a unique common channel frame format and one step multiplexing process. The channel frame format includes a plurality of data bit positions and a plurality of overhead bit positions. The number of data bit positions used is dependent on the particular incoming signal. Similarly, the number of frames generated during a specific common framing interval is dependent on the digital transmission bit rate of the particular signal. Specifically, the number of channel frames generated during the common channel frame interval is dependent on a number of equivalent so-called lowest transmission bit rate signals included in the particular signal being formatted. The overhead bits are distributed in the channel frame format. Digital words from the channel frames are inserted into predetermined groups of data word positions in a repetitive frame of a single transmission signal. The number of data words in a group is also dependent on the number of equivalent lowest transmission bit rate signals in the particular signal being combined.

摘要翻译： 通过采用唯一的公共信道帧格式和一步复用处理，将一个或多个数字传输比特率的多个数字信号组合成单个传输信号。 信道帧格式包括多个数据位位置和多个开销位位置。 使用的数据位位置的数量取决于特定的输入信号。 类似地，在特定公共成帧间隔期间产生的帧数取决于特定信号的数字传输比特率。 具体地，在公共信道帧间隔期间生成的信道帧的数量取决于被格式化的特定信号中包括的等效的所谓的最低传输比特率信号的数量。 开销位以通道帧格式分配。 来自信道帧的数字字被插入到单个发送信号的重复帧中的预定数据字位置组中。 组中的数据字的数量还取决于组合的特定信号中等效的最低传输比特率信号的数量。

公开(公告)号：US4740959A

公开(公告)日：1988-04-26

申请号：US813851

申请日：1985-12-27

申请人： Toru Kosugi ,  Katsutoshi Miyaji ,  Kouichi Sugama ,  Tamio Oonuma ,  Minoru Ishikawa

发明人： Toru Kosugi ,  Katsutoshi Miyaji ,  Kouichi Sugama ,  Tamio Oonuma ,  Minoru Ishikawa

IPC分类号： H04J3/16 ,  H04Q11/04

CPC分类号： H04J3/1641

摘要： A system for controlling a change of sequence order of channel data for a telecommunication terminal device including: a plurality of channel boards provided to a terminal device and each having transmitting and receiving portions; a multiplexing portion for multiplexing data sent from the channel boards so as to generate transmission data; a demultiplexing portion for demultiplexing reception data so as to send it to the channel boards; and a sequence order address signal generator for generating a sequence order address signal to a memory. The system includes a memory for receiving the sequence order signal and capable of rewriting data for changing a sequence order of channel data; a memory wire control portion for controlling data write access for the memory; and a channel pulse conversion portion for receiving data read out from the memory and for generating a channel pulse corresponding to the data read out from the memory, in which a data communication sequence order between the channel boards and the multiplexing portion is determined by the channel pulse.

摘要翻译： 一种用于控制通信终端设备的信道数据顺序改变的系统，包括：提供给终端设备并且各自具有发射和接收部分的多个信道板; 多路复用部分，用于复用从信道板发送的数据，以产生发送数据; 解复用部分，用于解复用接收数据，以将其发送到信道板; 以及用于向存储器生成序列顺序地址信号的序列顺序地址信号发生器。 该系统包括用于接收序列顺序信号并且能够重写用于改变频道数据的序列顺序的数据的存储器; 用于控制存储器的数据写入访问的存储器线控制部分; 以及通道脉冲转换部分，用于接收从存储器读出的数据，并产生与从存储器读出的数据相对应的通道脉冲，其中通道板和复用部分之间的数据通信顺序顺序由通道 脉冲。

公开(公告)号：US4697262A

公开(公告)日：1987-09-29

申请号：US758990

申请日：1985-07-25

申请人： Henry P. Segal ,  Carl A. DeWilde

发明人： Henry P. Segal ,  Carl A. DeWilde

IPC分类号： H04J3/06 ,  H04J3/16 ,  H04J3/22 ,  H04J3/12

CPC分类号： H04J3/1641 ,  H04J3/0629

摘要： A digital carrier channel bus interface module is disclosed for a multiplexer having a cross-connect bus system. Random access memory is loaded or unloaded by a serial-to-parallel or parallel-to-serial converter respectively with data in parallel format off a digital carrier line. A high speed digital carrier module controls high speed data transmission over the bus system to another digital carrier channel. Receive and transmit addresses are sequentially routed over receive and transmit address bus lines of the bus system so that bus drivers and bus receivers of the channel bus interface module may appropriately actuate the routing of data in parallel over the bus system.

摘要翻译： 公开了一种用于具有交叉连接总线系统的多路复用器的数字载波信道总线接口模块。 随机访问存储器分别由串行到并行或并行到串行转换器分别以与数字载波线并行的格式的数据加载或卸载。 高速数字载波模块通过总线系统控制高速数据传输到另一数字载波信道。 接收和发送地址通过总线系统的接收和发送地址总线顺序路由，使得通道总线接口模块的总线驱动器和总线接收器可以通过总线系统适当地启动数据的并行布线。

公开(公告)号：US4052567A

公开(公告)日：1977-10-04

申请号：US644102

申请日：1975-12-24

申请人： William Allan MacKay

发明人： William Allan MacKay

IPC分类号： G08C15/06 ,  H04J3/16 ,  H04J3/08

CPC分类号： H04J3/1641 ,  G08C15/06

摘要： A multiplexer receiver terminator is disclosed for connection to a multiplexer receiver in a system having a plurality of multiplexer receivers connected on a common communication line. Each of the multiplexer receivers is assigned a time period for reception relative to a multiplexer time clock. The improvement includes a counter circuit connected to the multiplexer time clock for providing a counter output upon the clock counter counting between two preselected clock counts which correspond to the time period assigned for reception of the multiplexer receiver. A line receiver is connected to the communication line for providing an output upon detecting a predetermined period of signal absence on the communication line. The line receiver output is connected to the counter for resetting the counter after the predetermined period of signal absence. The counter circuit is connected to the multiplexer receiver for enabling reception from the communication line only during an output of the counter circuit. The foregoing abstract is merely a resume of one general application, is not a complete discussion of all principles of operation or applications, and is not to be construed as a limitation on the scope of the claimed subject matter.