公开(公告)号：US20170220526A1

公开(公告)日：2017-08-03

申请号：US15500486

申请日：2015-04-16

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Brent Buchanan

IPC: G06F17/16 ,  G06F7/50 ,  G06F7/523 ,  G11C13/00

CPC classification number: G06F17/16 ,  G06F7/50 ,  G06F7/523 ,  G06F7/5443 ,  G06F2207/4802 ,  G11C7/1006 ,  G11C13/004 ,  G11C2213/77

Abstract: In one example in accordance with the present disclosure a resistive memory array is described. The array includes a number of resistive memory elements to receive a common-valued read signal. The array also includes a number of multiplication engines to perform a multiply operation by receiving a memory element output from a corresponding resistive memory element, receiving an input signal, and generating a multiplication output based on a received memory element output and a received input signal. The array also includes an accumulation engine to sum multiplication outputs from the number of multiplication engines.

公开(公告)号：US09691483B1

公开(公告)日：2017-06-27

申请号：US15270087

申请日：2016-09-20

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Brent Buchanan ,  John Paul Strachan ,  Le Zheng

IPC: G11C15/00 ,  G06F3/06

CPC classification number: G11C15/00

Abstract: In one aspect, techniques for providing a banked content addressable memory (CAM) with counters are provided. A dictionary word may be divided into a plurality of banks. A counter may be associated with each bank of the plurality of banks. The counter may count the number of times a segment of an input word aligned with the bank does not match. A scheduler may schedule comparison of banks with higher probability of not matching before banks with lower probability of not matching. The probability of not matching may be based on the counters.

公开(公告)号：US20170140817A1

公开(公告)日：2017-05-18

申请号：US15311594

申请日：2014-06-20

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Brent Buchanan ,  Richard James Auletta

IPC: G11C13/00

CPC classification number: G11C13/0059 ,  G11C13/0002 ,  G11C13/0064 ,  G11C13/0069

Abstract: In the examples provided herein, a voltage driver module applies an increasing voltage to a memristive memory cell until a resistance of the cell switches to a target resistance. A monitoring module monitors a switching voltage at which the resistance of the cell switches to the target resistance, or an application duration of the increasing voltage to the cell. Additionally, a controller performs an action to protect data stored by the cell upon determining that the switching voltage exceeds a target voltage.