公开(公告)号：US20220208954A1

公开(公告)日：2022-06-30

申请号：US17170975

申请日：2021-02-09

Applicant: Microchip Technology Incorporated

Inventor： Yaojian Leng ,  Justin Sato

IPC: H01L49/02

Abstract: A thin film resistor (TFR) module is formed in an integrated circuit device. The TFR module includes a TFR element connected between first and second vertically-extending TFR side contacts. The TFR element includes a base portion extending laterally between the TFR side contacts, and first and second TFR element end flanges projecting vertically from opposing ends of the base portion. The first TFR element end flange is formed on a sidewall of the first TFR side contact, and the second TFR element end flange is formed on a sidewall of the second TFR side contact. A first TFR head contacts the first TFR side contact and a top of the first TFR element end flange, and a second TFR head contacts the second TFR side contact and a top of the second TFR element end flange, thus defining two parallel conductive paths between the TFR element and each TFR head.

公开(公告)号：US20210384122A1

公开(公告)日：2021-12-09

申请号：US17117288

申请日：2020-12-10

Applicant: Microchip Technology Incorporated

Inventor： Yaojian Leng ,  Justin Sato

IPC: H01L23/522 ,  H01L23/532 ,  H01L49/02 ,  H01F27/28 ,  H01F27/32

Abstract: A low-resistance thick-wire integrated inductor may be formed in an integrated circuit (IC) device. The integrated inductor may include an elongated inductor wire defined by a metal layer stack including an upper metal layer, middle metal layer, and lower metal layer. The lower metal layer may be formed in a top copper interconnect layer, the upper metal layer may be formed in an aluminum bond pad layer, and the middle metal layer may comprise a copper tub region formed between the aluminum upper layer and copper lower layer. The wide copper region defining the middle layer of the metal layer stack may be formed concurrently with copper vias of interconnect structures in the IC device, e.g., by filling respective openings using copper electrochemical plating or other bottom-up fill process. The elongated inductor wire may be shaped in a spiral or other symmetrical or non-symmetrical shape.

公开(公告)号：US20210265263A1

公开(公告)日：2021-08-26

申请号：US16999358

申请日：2020-08-21

Applicant: Microchip Technology Incorporated

Inventor： Yaojian Leng

IPC: H01L23/522 ,  H01L49/02 ,  H01L21/768 ,  H01L23/532 ,  H01L23/00

Abstract: A method of forming a metal-insulator-metal (MIM) capacitor with copper top and bottom plates may begin with a copper interconnect layer (e.g., Cu MTOP) including a copper structure defining the capacitor bottom plate. A passivation region is formed over the bottom plate, and a wide top plate opening is etched in the passivation region, to expose the bottom plate. A dielectric layer is deposited into the top plate opening and onto the exposed bottom plate. Narrow via opening(s) are then etched in the passivation region. The wide top plate opening and narrow via opening(s) are concurrently filled with copper to define a copper top plate and copper via(s) in contact with the bottom plate. A first aluminum bond pad is formed on the copper top plate, and a second aluminum bond pad is formed in contact with the copper via(s) to provide a conductive coupling to the bottom plate.

公开(公告)号：US11094628B2

公开(公告)日：2021-08-17

申请号：US16549635

申请日：2019-08-23

Applicant: Microchip Technology Incorporated

Inventor： Yaojian Leng

IPC: H01L23/522 ,  H01L23/00 ,  H01L49/02 ,  H01L21/768

Abstract: In some embodiments, integrated inductors may be built using processes for forming interconnects of semiconductor devices without requiring additional process steps. Integrated inductor coils may be formed by, for example, shunting an overlying electrically conductive material, such as, for example, bond pad metals (e.g., aluminum and alloys thereof), to an underlying electrically conductive material, such as, for example, an uppermost layer of wiring formed using Damascene processes (e.g., utilizing copper and alloys thereof), without vias to interconnect the two materials. In some embodiments, integrated inductors formed utilizing such processes may have a symmetric spiral design.

公开(公告)号：US20210036059A1

公开(公告)日：2021-02-04

申请号：US17074848

申请日：2020-10-20

Applicant: Microchip Technology Incorporated

Inventor： Yaojian Leng ,  Justin Sato ,  Bomy Chen

IPC: H01L27/28

Abstract: An integrated circuit (IC) package product, e.g., system-on-chip (SoC) or system-in-package (SiP) product, may include at least one integrated inductor having a core magnetic field (B field) that extends parallel to the substrate major plane of at least one die or chiplet included in or mounted to the product, which may reduce the eddy currents within each die/chiplet substrate, and thereby reduce energy loss of the indictor. The IC package product may include a horizontally-extending IC package substrate, a horizontally-extending die mount base arranged on the IC package substrate, at least one die mounted to the die mount base in a vertical orientation, and an integrated inductor having a B field extending in a vertical direction parallel to the silicon substrate of each vertically-mounted die, thereby providing a reduced substrate loss in the integrated inductor, which provides an increased quality factor (Q) of the inductor.

公开(公告)号：US10818748B2

公开(公告)日：2020-10-27

申请号：US16034394

申请日：2018-07-13

Applicant: Microchip Technology Incorporated

Inventor： Yaojian Leng ,  Bonnie Hamlin ,  Andrew Taylor ,  Janet Vanderiet ,  Justin Sato

IPC: H01L49/02 ,  H01L21/285 ,  H01L21/311

Abstract: A method for manufacturing a thin film resistor (TFR) module includes forming a TFR element over a substrate; annealing the TFR element to reduce the temperature coefficient of resistance (TCR) of the TFR element; and after forming and annealing the TFR element, forming a pair of conductive TFR heads in contact with the TFR element. By forming the TFR element before the TFR heads, the TFR element may be annealed without affecting the TFR heads, and thus may be formed from various materials with different annealing properties, e.g., SiCCr and SiCr. Thus, the TFR element may be annealed to achieve a near 0 ppm TCR, without affecting the later-formed TFR heads. The TFR module may be formed using a damascene CMP approach and using only a single added mask layer. Further, vertically-extending “ridges” at edges of the TFR element may be removed or eliminated to further improve the TCR performance.

公开(公告)号：US20190386091A1

公开(公告)日：2019-12-19

申请号：US16037889

申请日：2018-07-17

Applicant: Microchip Technology Incorporated

Inventor： Justin Hiroki Sato ,  Yaojian Leng ,  Greg Stom

IPC: H01L49/02 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/3213 ,  H01L23/522 ,  H01L21/768 ,  H01L21/285

Abstract: A method for manufacturing a thin film resistor (TFR) module in an integrated circuit (IC) structure may include forming a trench in a dielectric region; forming a TFR element in the trench, the TFR element including a laterally-extending TFR region and a TFR ridge extending upwardly from a laterally-extending TFR region; depositing at least one metal layer over the TFR element; and patterning the at least one metal layer and etching the at least one metal layer using a metal etch to define a pair of metal TFR heads over the TFR element, wherein the metal etch also removes at least a portion of the upwardly-extending TFR ridge. The method may also include forming at least one conductive TFR contact extending through the TFR element and in contact with a respective TFR head to thereby increase a conductive path between the respective TFR head and the TFR element.