公开(公告)号：US09183140B2

公开(公告)日：2015-11-10

申请号：US14181252

申请日：2014-02-14

Applicant: Seagate Technology LLC

Inventor： Jeremy Isaac Nathaniel Werner ,  Leonid Baryudin ,  Timothy Lawrence Canepa ,  Earl T. Cohen

IPC: G06F12/02 ,  G06F11/10 ,  G06F11/20

CPC classification number: G06F12/0246 ,  G06F11/1044 ,  G06F11/108 ,  G06F11/2094

Abstract: Higher-level redundancy information computation enables a Solid-State Disk (SSD) controller to provide higher-level redundancy capabilities to maintain reliable operation in a context of failures of non-volatile (e.g. flash) memory elements during operation of an SSD. A first portion of higher-level redundancy information is computed using parity coding via an XOR of all pages in a portion of data to be protected by the higher-level redundancy information. A second portion of the higher-level redundancy information is computed using a weighted-sum technique, each page in the portion being assigned a unique non-zero “index” as a weight when computing the weighted-sum. Arithmetic is performed over a finite field (such as a Galois Field). The portions of the higher-level redundancy information are computable in any order, such as an order based on order of read operation completion of non-volatile memory elements.

Abstract translation: 高级冗余信息计算使得固态盘（SSD）控制器能够提供更高级别的冗余能力，以在SSD的运行期间在非易失性（例如闪存）存储器元件的故障的上下文中维持可靠的操作。 高级冗余信息的第一部分是使用奇偶校验编码来计算的，该奇偶编码经由待被较高级别冗余信息保护的数据的一部分中的所有页面的异或。 使用加权和技术来计算较高级冗余信息的第二部分，当计算加权和时，该部分中的每个页面被分配唯一的非零“索引”作为权重。 在有限域（例如伽罗瓦域）上执行算术。 高级冗余信息的部分可以以任何顺序计算，诸如基于非易失性存储器元件的读操作完成顺序的顺序。

公开(公告)号：US09035809B2

公开(公告)日：2015-05-19

申请号：US13651655

申请日：2012-10-15

Applicant: Seagate Technology LLC

Inventor： Earl T. Cohen

IPC: H03M7/30

CPC classification number: H03M7/3086

Abstract: An apparatus includes a first circuit and a second circuit. The first circuit may be configured to generate a reduced representation of an input sequence of characters by replacing a repetition of a sequence of one or more characters by a code representing the repetition of the sequence of one or more characters. The second circuit may be configured to generate a compressed representation of the input sequence of characters in response to the reduced representation of the input sequence of characters. The second circuit is generally configured to recognize the code representing the repetition of the sequence of one or more characters and take into account the repetition of the sequence of one or more characters during a compression operation.

Abstract translation: 一种装置包括第一电路和第二电路。 第一电路可以被配置为通过代表表示一个或多个字符的序列的重复的代码替换一个或多个字符的序列的重复来生成输入字符序列的缩小表示。 第二电路可以被配置为响应于输入的字符序列的减少的表示来生成输入的字符序列的压缩表示。 第二电路通常被配置为识别表示一个或多个字符的序列的重复的代码，并且在压缩操作期间考虑一个或多个字符的序列的重复。