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    Memory vulnerability mitigation
    2.
    发明授权
    Memory vulnerability mitigation 有权

    公开(公告)号：US12086072B1

    公开(公告)日：2024-09-10

    申请号：US16816044

    申请日：2020-03-11

    Applicant: Amazon Technologies, Inc.

    Inventor： Daniel John Farrell

    IPC: G06F12/00 ,  G06F11/10 ,  G06F12/02 ,  G06F12/1009

    CPC classification number: G06F12/1009 ,  G06F11/1044 ,  G06F12/023

    Abstract: Vulnerabilities to physical memory, such as server dynamic random access memory (DRAM) with error correction code (ECC) capability, can be mitigated though the use of guard pages allocated in that physical memory. Physical memory pages can be mapped to virtual memory pages of a contiguous virtual address space. When an error such as a bit flip is detected in a physical memory page, the data from that physical memory page can be copied to a protected page, such as a guard page or page isolated from other sensitive data. Information such as an error correction code (ECC) can be used to determine and correct the erroneous bit. The mappings in a related page table can be updated such that the same virtual pages or addresses are then mapped to the guard page that now includes the relevant data.

    Fuse logic to perform selectively enabled ecc decoding
    4.
    发明授权
    Fuse logic to perform selectively enabled ecc decoding 有权

    公开(公告)号：US12038804B2

    公开(公告)日：2024-07-16

    申请号：US18163722

    申请日：2023-02-02

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Beau D. Barry

    IPC: G06F11/00 ,  G06F11/10 ,  G06F11/22 ,  G06F11/30

    CPC classification number: G06F11/1044 ,  G06F11/221 ,  G06F11/2215 ,  G06F11/3027

    Abstract: Fuse logic is configured to selectively enable certain group of fuses of a fuse array to support one of column (or row) redundancy in one application or error correction code (ECC) operations in another application. For example, the fuse logic may decode the group of fuses to enable a replacement column (or row) of memory cells in one mode or application, and decodes a subset of the group of fuses to retrieve ECC data corresponding to a second group of fuses are encoded to enable a different replacement column or row of memory cells in a second mode or application. The fuse logic includes an ECC decode logic circuit that is selectively enabled to detect and correct errors in data encoded in the second group of fuses based on the ECC data encoded in the subset of fuses of the first group of fuses.

    Memory with address-selectable data poisoning circuitry, and associated systems, devices, and methods
    5.
    发明授权
    Memory with address-selectable data poisoning circuitry, and associated systems, devices, and methods 有权

    公开(公告)号：US12032834B2

    公开(公告)日：2024-07-09

    申请号：US17959131

    申请日：2022-10-03

    Applicant: Micron Technology, Inc.

    Inventor： Joshua E. Alzheimer ,  Mow Yiak Goh ,  Loren J. Wooley

    IPC: G06F3/06 ,  G06F11/10

    CPC classification number: G06F3/0619 ,  G06F3/0629 ,  G06F3/0673 ,  G06F11/1044

    Abstract: Memory with address-selectable data poisoning circuitry is disclosed herein. In one embodiment, a memory device comprises circuitry operably connected to a memory array. The circuitry can include memory row address registers and/or memory column address registers. Standard access commands or mode register write commands can be used to load a memory row address or a memory column address into the memory row address registers or the memory column address registers, respectively. During a read operation directed to a second memory row and/or column of the memory array, the circuitry can compare the second memory row to the first memory row and/or the second memory column to the first memory column, and can poison a data bit read from the memory array before the data bit is output from the memory device when the first and second memory row addresses match and/or when the first and second memory column addresses match.

    Memory including error correction circuit and operation method of memory
    6.
    发明授权
    Memory including error correction circuit and operation method of memory 有权

    公开(公告)号：US12032439B2

    公开(公告)日：2024-07-09

    申请号：US18104713

    申请日：2023-02-01

    Applicant: SK hynix Inc.

    Inventor： Gang Sik Lee

    IPC: G06F11/10 ,  G11C29/52

    CPC classification number: G06F11/1044 ,  G11C29/52

    Abstract: A memory includes: a memory core including memory regions; a refresh-excluded region storing circuit storing therein information on a refresh-excluded region on which a refresh operation is not to be performed among the memory regions; an error correction circuit correcting an error in data read from the memory core based on an error correction code read from the memory core; an error check operation control circuit performing an error check operation of checking an error in the read data by using the error correction circuit; a bad region classifying circuit classifying a selected memory region as a bad region based on an error, which is detected in data read from the selected memory region during the error check operation; and a blocking circuit preventing the bad region classifying circuit from classifying the refresh-excluded region as a bad region based on the information.

    STORAGE SYSTEM AND METHOD FOR HIDING ERROR CHECKING AND CORRECTING (ECC) ENCODING DELAY
    9.
    发明公开
    STORAGE SYSTEM AND METHOD FOR HIDING ERROR CHECKING AND CORRECTING (ECC) ENCODING DELAY 审中-公开

    公开(公告)号：US20240126645A1

    公开(公告)日：2024-04-18

    申请号：US18273031

    申请日：2021-12-03

    Applicant: METAX INTEGRATED CIRCUITS (SHANGHAI) CO., LTD.

    Inventor： Ying LI

    IPC: G06F11/10

    CPC classification number: G06F11/1044

    Abstract: A storage system and method for hiding Error Checking and Correcting (ECC) encoding delay are disclosed. An output of a data register is configured to be two data streams. One data stream transmits an input write data and an ECC check code to the SRAM through an ECC encoding module and an intermediate write data register, and the other data stream inputs the input write data to a read data selector through a bypass register module through the intermediate write data register and the bypass register module. The other input of the read data selector is the data set whose errors have been checked and corrected by the ECC encoding error checking module which reads the data set from the SRAM. The read data selector is configured to transmit the selected input data to the read data register. According to the present disclosure, when data at the address is read right after the data is written to the address, the read data selector selects to output the write data received from the bypass register module; but when data is written to an address but data at an other address is read, the read data selector selects to output the data set whose errors have been checked and corrected by the ECC encoding error checking module which reads the data set from the SRAM.

    QUANTUM ERROR CORRECTION
    10.
    发明公开
    QUANTUM ERROR CORRECTION 审中-公开

    公开(公告)号：US20240078152A1

    公开(公告)日：2024-03-07

    申请号：US18220752

    申请日：2023-07-11

    Applicant: Google LLC

    Inventor： Austin Greig Fowler

    IPC: G06F11/10 ,  G06F15/16 ,  G06N10/00 ,  G06N10/70

    CPC classification number: G06F11/1044 ,  G06F15/16 ,  G06N10/00 ,  G06N10/70

    Abstract: Apparatus for quantum error correction is disclosed. The apparatus includes an array of processing cores, each processing core comprising: a processor on a first chip; and a processor cache on the first chip; and a bus for interconnecting neighbouring processing cores in the array of processing cores; wherein each processing core includes: control code which, when executed by the processor, causes the processor to access a processor cache of at least one neighbouring processing core.

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