公开(公告)号：US5729166A

公开(公告)日：1998-03-17

申请号：US660779

申请日：1996-06-10

申请人： Michael R. May ,  Michael D. Cave

发明人： Michael R. May ,  Michael D. Cave

IPC分类号： H03K5/00 ,  H03K3/72

CPC分类号： H03K5/00006

摘要： A frequency multiplication circuit (10) includes a periodic interval selector (12) and a delay element (28) to produce an output signal (26) in phase with, and at a frequency multiple of a reference signal (18). During a first time interval, the periodic interval selector (12) bases the output signal (26) on the reference signal (18). During a second time interval, the periodic interval selector (12) bases the output signal (26) on a delayed signal (22) produced by the delay element (14) based upon the output signal (26). Feedback from the output of the periodic interval selector (12) through the delay element (14) and the operation of the periodic interval selector (12) causes the output signal (26) to be in phase with, and at a frequency multiple of the reference signal (18). Delay adjuster (52) adjusts delay produced by the delay element (14) to adjust the output signal (26) to cause the output signal (26) to have a desired duty cycle consistency. Periodic interval selector (12) and delay adjuster (52) may be adjusted as well as to adjust a frequency multiplication ratio of the frequency multiplication circuit (10). Delay element (14) may be implemented with digital circuit elements such as inverters, other logic gates, or individual circuit elements operably coupled to produce a controllable variable delay.

摘要翻译： 倍频电路（10）包括周期性间隔选择器（12）和延迟元件（28），以产生与参考信号（18）同相和频率倍数的输出信号（26）。 在第一时间间隔期间，周期性间隔选择器（12）将输出信号（26）基于参考信号（18）。 在第二时间间隔期间，周期间隔选择器（12）基于输出信号（26）将输出信号（26）基于由延迟元件（14）产生的延迟信号（22）。 来自周期性间隔选择器（12）的输出到延迟元件（14）的反馈和周期性间隔选择器（12）的操作使得输出信号（26）与 参考信号（18）。 延迟调整器（52）调整由延迟元件（14）产生的延迟以调整输出信号（26），使得输出信号（26）具有期望的占空比一致性。 可以调节周期性间隔选择器（12）和延迟调节器（52）以及调节倍频电路（10）的倍频比。 延迟元件（14）可以用诸如逆变器，其它逻辑门或可操作地耦合以产生可控可变延迟的单独电路元件的数字电路元件来实现。