公开(公告)号：US06313770B1

公开(公告)日：2001-11-06

申请号：US09596152

申请日：2000-06-15

申请人： Michael D Cave

发明人： Michael D Cave

IPC分类号： H03M152

CPC分类号： H03M1/1245

摘要： In accordance with a specific embodiment of the present invention, a system is disclosed having an analog to digital converter and control module. The analog-to-digital converter includes an analog input, digital output, and control input. The control input of the analog-to-digital converter is connected to a pulse width modulated output of the control module which provides an offset pulse width modulated signal. During a first portion of the offset pulse width modulated signal a sampling capacitor is charged. During a second portion of the offset pulse width modulated signal an integration capacitor is charged.

摘要翻译： 根据本发明的具体实施例，公开了具有模数转换器和控制模块的系统。 模数转换器包括模拟输入，数字输出和控制输入。 模数转换器的控制输入连接到控制模块的脉宽调制输出端，该输出端提供偏移脉冲宽度调制信号。 在偏移脉冲宽度调制信号的第一部分期间，采样电容器被充电。 在偏移脉冲宽度调制信号的第二部分期间，积分电容器被充电。

公开(公告)号：US5729166A

公开(公告)日：1998-03-17

申请号：US660779

申请日：1996-06-10

申请人： Michael R. May ,  Michael D. Cave

发明人： Michael R. May ,  Michael D. Cave

IPC分类号： H03K5/00 ,  H03K3/72

CPC分类号： H03K5/00006

摘要： A frequency multiplication circuit (10) includes a periodic interval selector (12) and a delay element (28) to produce an output signal (26) in phase with, and at a frequency multiple of a reference signal (18). During a first time interval, the periodic interval selector (12) bases the output signal (26) on the reference signal (18). During a second time interval, the periodic interval selector (12) bases the output signal (26) on a delayed signal (22) produced by the delay element (14) based upon the output signal (26). Feedback from the output of the periodic interval selector (12) through the delay element (14) and the operation of the periodic interval selector (12) causes the output signal (26) to be in phase with, and at a frequency multiple of the reference signal (18). Delay adjuster (52) adjusts delay produced by the delay element (14) to adjust the output signal (26) to cause the output signal (26) to have a desired duty cycle consistency. Periodic interval selector (12) and delay adjuster (52) may be adjusted as well as to adjust a frequency multiplication ratio of the frequency multiplication circuit (10). Delay element (14) may be implemented with digital circuit elements such as inverters, other logic gates, or individual circuit elements operably coupled to produce a controllable variable delay.

摘要翻译： 倍频电路（10）包括周期性间隔选择器（12）和延迟元件（28），以产生与参考信号（18）同相和频率倍数的输出信号（26）。 在第一时间间隔期间，周期性间隔选择器（12）将输出信号（26）基于参考信号（18）。 在第二时间间隔期间，周期间隔选择器（12）基于输出信号（26）将输出信号（26）基于由延迟元件（14）产生的延迟信号（22）。 来自周期性间隔选择器（12）的输出到延迟元件（14）的反馈和周期性间隔选择器（12）的操作使得输出信号（26）与 参考信号（18）。 延迟调整器（52）调整由延迟元件（14）产生的延迟以调整输出信号（26），使得输出信号（26）具有期望的占空比一致性。 可以调节周期性间隔选择器（12）和延迟调节器（52）以及调节倍频电路（10）的倍频比。 延迟元件（14）可以用诸如逆变器，其它逻辑门或可操作地耦合以产生可控可变延迟的单独电路元件的数字电路元件来实现。

公开(公告)号：US06654900B1

公开(公告)日：2003-11-25

申请号：US09553129

申请日：2000-04-19

申请人： Michael D Cave

发明人： Michael D Cave

IPC分类号： G06F106

CPC分类号： G06F1/06 ,  H03K5/00006 ,  H03K5/1565 ,  H03K2005/00039

摘要： A method and apparatus for producing multiple clock signals having controlled duty cycles and phase relationships includes processing that begins by generating a plurality of delayed clock signals from an input clock signal based on a delay control signal. The processing then continues by producing a first multiple clock signal from a first set of a plurality of delayed clock signals and the input clock signal. The processing then continues by producing a second multiplied clock signal from a second set of the plurality of delayed clock signals, where the second multiplied clock signal is delayed from the first multiplied clock signal in accordance with a delay of at least one of the delayed clock signals. The processing then continues by generating the delayed control signal based on the first multiplied clock signal, where the delay control signal controls delays of the plurality of delayed clock signals.

摘要翻译： 一种用于产生具有受控占空比和相位关系的多个时钟信号的方法和装置包括基于延迟控制信号从输入时钟信号产生多个延迟时钟信号开始的处理。 然后通过从多个延迟时钟信号的第一组和输入时钟信号产生第一多个时钟信号来继续处理。 然后通过从多个延迟时钟信号的第二组产生第二倍频时钟信号来继续处理，其中根据延迟时钟中的至少一个的延迟，第二相乘时钟信号从第一倍增时钟信号延迟 信号。 然后通过基于第一倍时钟信号产生延迟的控制信号继续处理，其中延迟控制信号控制多个延迟的时钟信号的延迟。

公开(公告)号：US5563779A

公开(公告)日：1996-10-08

申请号：US349291

申请日：1994-12-05

申请人： Michael D. Cave ,  Mauricio A. Zavaleta

发明人： Michael D. Cave ,  Mauricio A. Zavaleta

IPC分类号： H02M3/07 ,  H02M3/18 ,  H02M7/00

CPC分类号： H02M3/07

摘要： A regulated supply (10) includes a charge pump (12), an output (14), a sensing circuit (16), and a control circuit (18). The charge pump (12) includes a variable capacitor (33) whose capacitance C.sub.v may be varied to compensate for changing loads and input power supply levels. The sensing circuit (16) senses the voltage level at the output (14) and provides feedback signals (66) and (68) to the control circuit (18). The voltage at the output (14) is dependent upon the capacitance C.sub.v of the variable capacitor (33). Therefore, responsive to the feedback signals (66) and (68) from the sensing circuit, the control circuit (18) varies the capacitance C.sub.v of the variable capacitor (33). The control circuit (18) then may vary the value of C.sub.v in a step-like manner to correct for the voltage at the output (14).

摘要翻译： 调节电源（10）包括电荷泵（12），输出（14），感测电路（16）和控制电路（18）。 电荷泵（12）包括可变电容器（33），其可以改变电容Cv以补偿变化的负载和输入电源电平。 感测电路（16）感测输出端（14）处的电压电平，并向控制电路（18）提供反馈信号（66）和（68）。 输出（14）处的电压取决于可变电容器（33）的电容Cv。 因此，响应于来自感测电路的反馈信号（66）和（68），控制电路（18）改变可变电容器（33）的电容Cv。 然后，控制电路（18）可以以类似步骤的方式改变Cv的值以校正输出端（14）处的电压。

公开(公告)号：US5966054A

公开(公告)日：1999-10-12

申请号：US15846

申请日：1998-01-29

申请人： Michael R. May ,  Michael D. Cave ,  Joseph C. Fong

发明人： Michael R. May ,  Michael D. Cave ,  Joseph C. Fong

IPC分类号： H03B5/12 ,  H03B5/04 ,  H03B5/36

CPC分类号： H03B5/366

摘要： A method that includes the steps of producing a digital code (104) based at least in part on an integrated circuit capacitance and adjusting a frequency of the clocking signal in response to the digital code (106). A method that includes the steps of in a first mode of operation, producing a fixed frequency clocking signal, the fixed frequency clocking signal having a frequency tolerance less than 20 units per million and, in a second mode of operation, producing a variable frequency clocking signal, the variable frequency clocking signal having a frequency variability range greater than 200 units per million. An apparatus for providing a clocking signal includes a tuner circuit (12) and an oscillator circuit (16) responsive to the tuner circuit (12). The tuner circuit (12) is responsive to a clock signal source (38), an integrated circuit capacitance, and a reference resistor (18). The tuner circuit (12) produces a digital code signal. (22) The oscillator circuit (16) includes at least one adjustable integrated circuit capacitor (30, 32) responsive to the digital code signal (22) and is capable of producing the clocking signal.

摘要翻译： 一种方法，其包括以下步骤：至少部分地基于集成电路电容产生数字代码（104），并响应于所述数字代码（106）调整所述计时信号的频率。 一种方法，其包括以下步骤：在第一操作模式中产生固定频率时钟信号，所述固定频率时钟信号具有小于每百万个百万个单位的频率容限，并且在第二操作模式中，产生可变频率时钟 信号，可变频率时钟信号的频率变化范围大于200个百万分之一。 用于提供时钟信号的装置包括调谐器电路（12）和响应于调谐器电路（12）的振荡器电路（16）。 调谐器电路（12）响应时钟信号源（38），集成电路电容和参考电阻（18）。 调谐器电路（12）产生数字码信号。 （22）响应于数字码信号（22），振荡器电路（16）包括至少一个可调整的集成电路电容器（30,32），并且能够产生时钟信号。

公开(公告)号：US07596127B1

公开(公告)日：2009-09-29

申请号：US09999593

申请日：2001-10-31

申请人： Michael R. May ,  Michael D. Cave

发明人： Michael R. May ,  Michael D. Cave

IPC分类号： H04J1/00

CPC分类号： H04L5/0007 ,  H04L5/0044 ,  H04L5/006

摘要： Poor transmission reliability is identified in a data channel. Multiple frequency carriers are used to transmit different sets of data within the data channel. A frequency bin is assigned to each frequency carrier. The frequency bins are used to provide data to each frequency carrier. A transmission power assigned to each frequency carrier may be insufficient to overcome noise in the data channel when all the frequency bins are used to transfer data concurrently. The number of frequency bins associated with frequency carriers of the data channel are reduced. Power is increased to the available frequency bins to improve transmission reliability. The available frequency bins are allocated across the data channel according to a pattern used to spread allocated transmission power across the data channel. The frequency bin pattern is rotated among available frequency bins of the data channel, allowing different frequency bins to be used for each transmission. Accordingly, a power spectral density associated with the transmissions remains within a nominal power spectral density.

摘要翻译： 在数据通道中识别出差的传输可靠性。 多个频率载波用于在数据信道内传输不同的数据集。 频率仓被分配给每个频率载波。 频率仓用于向每个频率载波提供数据。 分配给每个频率载波的传输功率可能不足以克服当所有频率仓同时传送数据时数据信道中的噪声。 与数据信道的频率载波相关联的频率仓的数量减少。 功率增加到可用的频率箱，以提高传输可靠性。 根据用于在数据信道上扩展分配的传输功率的模式，可用的数据信道分配在数据信道上。 频率仓模式在数据通道的可用频率仓之间旋转，允许不同的频率仓用于每次发送。 因此，与传输相关联的功率谱密度保持在标称功率谱密度内。

公开(公告)号：US5563533A

公开(公告)日：1996-10-08

申请号：US396390

申请日：1995-02-28

申请人： Michael D. Cave ,  Mauricio A. Zavaleta

发明人： Michael D. Cave ,  Mauricio A. Zavaleta

IPC分类号： H03K5/08 ,  H03K3/356 ,  H03K5/24 ,  H03K3/023 ,  H03K3/037 ,  H03K5/22

CPC分类号： H03K3/356113 ,  H03K5/249

摘要： A comparator (10) provides a high speed comparison between at least two input signals and includes at least two stages (12) and (14). Each stage (12 and 14) includes a pair of transistors (24), a complementary pair of transistors (28) and an enabling transistor (26). The stages are coupled to provide positive feedback back to the first stage (12). A controller (15) operably couples to the enabling transistors. When the first input signal (16) is at a higher voltage level than the second input signal (18), the first comparison output (20) goes low. Conversely, when the second input signal (18) is at a higher voltage level than the first input signal (16), the second comparison output (22) goes low. When the first comparison output (20) goes low, the second enabling transistor (34) is disabled by the controller (15). When the second comparison output goes low, the first enabling transistor (26) is disabled by the controller (15).

摘要翻译： 比较器（10）提供至少两个输入信号之间的高速比较，并且包括至少两个级（12）和（14）。 每个级（12和14）包括一对晶体管（24），一对互补晶体管（28）和使能晶体管（26）。 这些级耦合以提供回到第一级的正反馈（12）。 控制器（15）可操作地耦合到使能晶体管。 当第一输入信号（16）处于比第二输入信号（18）更高的电压电平时，第一比较输出（20）变低。 相反，当第二输入信号（18）处于比第一输入信号（16）更高的电压电平时，第二比较输出（22）变低。 当第一比较输出（20）变低时，第二使能晶体管（34）被控制器（15）禁用。 当第二比较输出变低时，第一使能晶体管（26）被控制器（15）禁用。

公开(公告)号：US5777522A

公开(公告)日：1998-07-07

申请号：US775991

申请日：1997-01-03

申请人： Mathew A. Rybicki ,  Michael D. Cave

发明人： Mathew A. Rybicki ,  Michael D. Cave

IPC分类号： H03B1/00 ,  H03B5/32 ,  H03B5/36 ,  H03K3/03 ,  H03L7/081 ,  H03L7/099 ,  H03L7/00 ,  H03B5/20

CPC分类号： H03L7/081 ,  H03K3/0307 ,  H03L7/099 ,  H03B2200/0062 ,  H03B2201/0208 ,  H03B2201/0291 ,  H03B5/32 ,  H03B5/364 ,  H03B5/368 ,  H03J2200/10

摘要： A capacitor (200) having an actual physical capacitance value of Cact and is coupled to an oscillator (36). The oscillation frequency of the oscillator (36) can be changed by changing the effective capacitance of the capacitor (200). The actual capacitance (Cact) of capacitor (200) can be altered to appear to be any effective capacitance (Ceff) between zero and a value much greater than Cact by using a Miller effect. In order to alter the effective capacitance of the capacitor (200), a representation of the output osculation signal (16) is provided to a frequency adjust stage (22). The frequency adjust stage either passed the signal (16) with 0.degree. phase shift or with 180.degree. phase shift. In addition to shifting the phase, the stage (22) will amplify or attenuate the signal (16) to result in the phase shifted and amplified/attenuated frequency adjusting signal (24). By providing the signals (16 and 24) to opposite ends of the capacitor (200), Miller affect will alter the effective capacitance of the capacitor (200) thereby altering a frequency of the oscillator (36).

摘要翻译： 一种具有实际物理电容值Cact并耦合到振荡器（36）的电容器（200）。 可以通过改变电容器（200）的有效电容来改变振荡器（36）的振荡频率。 电容器（200）的实际电容（Cact）可以通过使用米勒效应来改变，使其看上去在零和通过Cact大得多的值之间的任何有效电容（Ceff）。 为了改变电容器（200）的有效电容，输出信号信号（16）的表示被提供给频率调节级（22）。 频率调节级通过0°相移或180°相移的信号（16）。 除了移相之外，级（22）将放大或衰减信号（16）以产生相移和放大/衰减的频率调整信号（24）。 通过将信号（16和24）提供给电容器（200）的相对端，米勒的影响将改变电容器（200）的有效电容，从而改变振荡器（36）的频率。

公开(公告)号：US5727038A

公开(公告)日：1998-03-10

申请号：US707828

申请日：1996-09-06

申请人： Michael R. May ,  Michael D. Cave

发明人： Michael R. May ,  Michael D. Cave

IPC分类号： H03D13/00 ,  H03L7/089 ,  H03L7/093 ,  H03L7/099 ,  H03L7/191 ,  H03D3/24

CPC分类号： H03D13/004 ,  H03L7/089 ,  H03L7/0997 ,  H03L7/191 ,  H03L2207/50 ,  H03L7/093

摘要： A phase locked loop (10) with a phase detector (11), a digital loop filter (12), a digital controlled oscillator (13) and a divide-by-N circuit (14) generates a periodic signal which has a predetermined phase and voltage related to a reference clock signal. A phase and frequency detector (21) outputs an average of error between a feedback delay clock and a reference clock to the digital loop filter (12). The digital loop filter (12) processes the phase detector (11) output and the inband quantization noise utilizing a sigma delta converter. The digital loop filter (12) utilizes a non binary weight scheme to minimize the number of bits changing states. The digital controlled oscillator (13) generates a loop clock signal utilizing a plurality of digital programmable delay elements. A divide-by-N circuit (14) performs a divide by 2560.

摘要翻译： 具有相位检测器（11），数字环路滤波器（12），数字控制振荡器（13）和N分频电路（14）的锁相环（10）产生具有预定相位的周期信号 和与参考时钟信号有关的电压。 相位和频率检测器（21）将反馈延迟时钟和参考时钟之间的误差的平均值输出到数字环路滤波器（12）。 数字环路滤波器（12）利用Σ-Δ转换器处理相位检测器（11）输出和带内量化噪声。 数字环路滤波器（12）利用非二进制加权方案来最小化位数改变状态。 数字控制振荡器（13）利用多个数字可编程延迟元件产生环路时钟信号。 N分频电路（14）执行除法2560。

公开(公告)号：US5596301A

公开(公告)日：1997-01-21

申请号：US435104

申请日：1995-05-04

申请人： Mathew A. Rybicki ,  Michael D. Cave

发明人： Mathew A. Rybicki ,  Michael D. Cave

IPC分类号： H03K3/012 ,  H03K3/03 ,  H03B5/32 ,  H03L7/099

CPC分类号： H03K3/012 ,  H03K3/03

摘要： The output frequency (14) of an oscillator circuit (10) can be controlled by replacing at least one of the reactive components (40), such as a capacitor or inductor, with a synthesized element (22). The synthesized element creates a signal that corresponds to the response of the reactive component it is replacing. The synthesized element may be a current source (44), such as a field effect transistor, that is capable of operating at low voltages.

摘要翻译： 振荡电路（10）的输出频率（14）可以通过用合成元件（22）代替诸如电容器或电感器的无功分量（40）中的至少一个来控​​制。 合成元素创建一个信号，该信号对应于其正在替换的无功元件的响应。 合成元件可以是能够在低电压下操作的电流源（44），例如场效应晶体管。