公开(公告)号：US06636377B1

公开(公告)日：2003-10-21

申请号：US09608573

申请日：2000-06-30

申请人： Jie Yu ,  David B. Joan

发明人： Jie Yu ,  David B. Joan

IPC分类号： G11B5596

CPC分类号： G11B5/59605 ,  G11B5/5547

摘要： A method of tuning a servo control system in a disk drive that implements seeks using a the feed-forward command effort signal uffwd and a PES reference signal r that were designed to be compatible with one another on the basis of a modeled frequency response G0(z) that is different from an actual frequency response G(z). The steps includes scaling the feed-forward command effort signal uffwd to substantially achieve a zero velocity condition at an end of the seek; scaling the feed-forward command effort signal uffwd to substantially achieve an on-target condition at the end of the seek; and modifying the PES reference signal r such that it substantially varies in unison with the indicated PES signal y during the seek

摘要翻译： 一种调整磁盘驱动器中的伺服控制系统的方法，该方法使用基于建模的频率响应G0（被设计为彼此兼容）的前馈命令工作信号uffwd和PES参考信号r来实现寻道 z）与实际频率响应G（z）不同。 这些步骤包括缩放前馈命令努力信号uffwd以在搜索结束时基本上实现零速度条件; 缩放前馈命令努力信号uffwd以在搜索结束时基本上实现目标条件; 以及修改PES参考信号r，使得其在搜索期间与所指示的PES信号y一致地基本上变化

公开(公告)号：US06316304B1

公开(公告)日：2001-11-13

申请号：US09614553

申请日：2000-07-12

申请人： Yelehanka Ramachandramurthy Pradeep ,  Jie Yu ,  Tjin Tjin Tjoa ,  Kelvin Wei Loong Loh

发明人： Yelehanka Ramachandramurthy Pradeep ,  Jie Yu ,  Tjin Tjin Tjoa ,  Kelvin Wei Loong Loh

IPC分类号： H01L218238

CPC分类号： H01L21/8238 ,  H01L21/823468

摘要： A method is described for forming gate sidewall spacers having different widths. The variation in spacer width allows for optimization of the MOSFET characteristics by changing the dimensions of the lightly doped source/drain extensions. The process is achieved using a method where the gate structure, comprising the gate electrode and gate oxide, is formed by conventional techniques upon a substrate. Lightly doped source drain extensions are implanted into the substrate not protected by the gate structure. The exposed substrate and gate structure are then covered with an insulating liner layer. This is followed by an etch stop layer deposition over the insulating liner layer. A first spacer oxide layer is then deposited over the etch stop layer. Areas where thicker spacers are desired are masked, and the unmasked spacer oxide layer is removed. The mask is then stripped away and additional spacer oxide is grown over the entire surface. The result is a thicker oxide in the areas protected by the mask during the previous etch step. The oxide is anisotropically etched and spacers are formed along the gate sidewalls. The spacers are wider in the areas with the thicker oxide. The process continues by etching the etch stop layer not protected by the spacers. The source and drain electrodes are then formed by implanting ions into the substrate not protected by the gate structure and sidewall spacers. Adjustment of the spacer width is accomplished by adjusting the total thickness of the etch stop and spacer oxide layers. Spacer width variation is controlled by changing the deposition thickness of the first spacer oxide layer.

摘要翻译： 描述了形成具有不同宽度的栅极侧壁间隔物的方法。 间隔宽度的变化允许通过改变轻掺杂源极/漏极延伸部分的尺寸来优化MOSFET特性。 该方法使用其中通过常规技术在衬底上形成包括栅电极和栅极氧化物的栅极结构的方法来实现。 轻掺杂的源极漏极延伸部被注入到不被栅极结构保护的衬底中。 然后用绝缘衬垫层覆盖暴露的衬底和栅极结构。 之后是绝缘衬垫层上的蚀刻停止层沉积。 然后在蚀刻停止层上沉积第一间隔氧化物层。 掩蔽需要较厚间隔物的区域，并且去除未掩蔽的间隔氧化物层。 然后剥去掩模，并在整个表面上生长附加的间隔氧化物。 结果是在先前蚀刻步骤期间由掩模保护的区域中较厚的氧化物。 氧化物被各向异性蚀刻，并且沿着栅极侧壁形成间隔物。 在具有较厚氧化物的区域中，间隔物较宽。 该过程通过蚀刻不被间隔物保护的蚀刻停止层而继续。 然后通过将离子注入到不被栅极结构和侧壁间隔物保护的衬底中来形成源极和漏极。 通过调整蚀刻停止层和间隔氧化物层的总厚度来实现间隔物宽度的调整。 通过改变第一间隔氧化物层的沉积厚度来控制间隔宽度变化。