公开(公告)号：US08065506B2

公开(公告)日：2011-11-22

申请号：US12193455

申请日：2008-08-18

申请人： Jinwen Xi ,  Roman Staszewski ,  Thang Minh Tran

发明人： Jinwen Xi ,  Roman Staszewski ,  Thang Minh Tran

IPC分类号： G06F17/00

CPC分类号： G06F9/3885 ,  G06F9/30036

摘要： This invention is an application specific integrated processor to implement the complete fixed-rate DRX signal processing paths (FDRX) for a reconfigurable processor-based multi-mode 3G wireless application. This architecture is based on the baseline 16-bit RISC architecture with addition functional blocks (ADU) tightly coupled with the based processor's data path. Each ADU accelerates a computation-intensive tasks in FDRX signal path, such as multi-tap FIRs, IIRs, complex domain and vectored data processing. The ADUs are controlled through custom instructions based on the load/store architecture. The whole FDRX data path can be easily implemented by the software employing these custom instructions.

摘要翻译： 本发明是一种专用集成处理器，用于实现用于可重新配置的基于处理器的多模3G无线应用的完整固定速率DRX信号处理路径（FDRX）。 该架构基于16位RISC架构，附加功能块（ADU）与基于处理器的数据路径紧密耦合。 每个ADU加速FDRX信号路径中的计算密集型任务，如多抽头FIR，IIR，复杂域和矢量数据处理。 ADU通过基于加载/存储架构的定制指令进行控制。 整个FDRX数据路径可以通过使用这些定制指令的软件轻松实现。

公开(公告)号：US20110208950A1

公开(公告)日：2011-08-25

申请号：US13053000

申请日：2011-03-21

申请人： Thang Minh Tran ,  Raul A. Garibay, JR. ,  James Nolan Hardage

发明人： Thang Minh Tran ,  Raul A. Garibay, JR. ,  James Nolan Hardage

IPC分类号： G06F9/30

CPC分类号： G06F9/3826 ,  G06F9/3838

摘要： A method of instruction issue (3200) in a microprocessor (1100, 1400, or 1500) with execution pipestages (E1, E2, etc.) and that executes a producer instruction Ip and issues a candidate instruction I0 (3245) having a source operand dependency on a destination operand of instruction Ip. The method includes issuing the candidate instruction I0 as a function (1720, 1950, 1958, 3235) of a pipestage EN(I0) of first need by the candidate instruction for the source operand, a pipestage EA(Ip) of first availability of the destination operand from the producer instruction, and the one execution pipestage E(Ip) currently associated with the producer instruction. A method of data forwarding (3300) in a microprocessor (1100, 1400, or 1500) having a pipeline (1640) having pipestages (E1, E2, etc.), wherein the method includes scoreboarding information E(Ip) (1710, 2220) to represent a changing pipestage position for data from a producer instruction Ip, and selectively forwarding (2310, 3360) the data from the pipestage having the represented pipestage position E(Ip), based on the information (1710), to a receiving pipestage (1682, E1) for a dependent instruction. Wireless communications devices (1010, 1010′, 1040, 1050, 1060, 1080), systems, circuits, devices, scoreboards (1700.N), processes and methods of operation, processes and articles of manufacture (FIGS. 13-16), are also disclosed.

摘要翻译： 一种在具有执行分支（E1，E2等）的微处理器（1100,1400或1500）中执行指令发出（3200）的方法，并且执行生成器指令Ip并发出具有源操作数的候选指令I0（3245） 依赖于指令Ip的目标操作数。 该方法包括作为源操作数的候选指令首先需要的分支管理EN（I0）的函数（1720,195，...，1935，3235）发出候选指令I0，以及源操作数的第一可用性的分支EA（Ip） 来自生产者指令的目的地操作数和当前与生产者指令相关联的一个执行管道E（Ip）。 一种具有具有分支（E1，E2等）的流水线（1640）的微处理器（1100,1400或1500）中的数据转发（3300）方法，其中该方法包括记分板信息E（Ip）（1710,2220 ）表示来自生产者指令Ip的数据的变化的管道位置，并且基于所述信息（1710）从具有所述管道位置E（Ip）的所述管道选择性地将（2310,3360）的数据转发到接收管道 （1682，E1）用于依赖指令。 无线通信设备（1010,1010'，1040,1050,1060,1080），系统，电路，设备，记分板（1700.N），操作过程和方法，过程和制品（图13-16） 也被披露。

公开(公告)号：US20170115686A1

公开(公告)日：2017-04-27

申请号：US14919760

申请日：2015-10-22

申请人： Thang Minh Tran

发明人： Thang Minh Tran

IPC分类号： G06F1/12

CPC分类号： G06F1/12

摘要： A digital circuitry comprising a processing unit that receives a first clock and comprising of a first self-clock circuitry that generates a first internal clock; wherein the said first self-clock circuitry further comprises of a mechanism to select between the said first clock and the first internal clock of the said processing unit for clock edge synchronization.

公开(公告)号：US07475231B2

公开(公告)日：2009-01-06

申请号：US11273691

申请日：2005-11-14

申请人： Thang Minh Tran

发明人： Thang Minh Tran

IPC分类号： G06F9/42

CPC分类号： G06F9/381 ,  G06F9/325 ,  G06F9/3806

摘要： A system and a method to identify a conditional branch instruction having a program counter and a target address, and increment a loop count each time the program counter and the target address equal a stored program counter and a target address. The system and method additionally includes assignment of a start loop pointer and an end loop pointer, based on an offset, when the loop count is equal to a threshold value, and capturing instructions for a loop, as defined by the start loop pointer and the end loop pointer, in an instruction queue.

摘要翻译： 一种用于识别具有程序计数器和目标地址的条件转移指令的系统和方法，并且每当程序计数器和目标地址等于存储的程序计数器和目标地址时，增加循环计数。 该系统和方法还包括当循环计数等于阈值时基于偏移量分配起始循环指针和结束循环指针，以及捕获由起始循环指针和 结束循环指针，在指令队列中。

公开(公告)号：US20090063820A1

公开(公告)日：2009-03-05

申请号：US12193455

申请日：2008-08-18

申请人： Jinwen Xi ,  Roman Staszewski ,  Thang Minh Tran

发明人： Jinwen Xi ,  Roman Staszewski ,  Thang Minh Tran

IPC分类号： G06F9/30

CPC分类号： G06F9/3885 ,  G06F9/30036

摘要： This invention is an application specific integrated processor to implement the complete fixed-rate DRX signal processing paths (FDRX) for a reconfigurable processor-based multi-mode 3G wireless application. This architecture is based on the baseline 16-bit RISC architecture with addition functional blocks (ADU) tightly coupled with the based processor's data path. Each ADU accelerates a computation-intensive tasks in FDRX signal path, such as multi-tap FIRs, IIRs, complex domain and vectored data processing. The ADUs are controlled through custom instructions based on the load/store architecture. The whole FDRX data path can be easily implemented by the software employing these custom instructions.

摘要翻译： 本发明是一种专用集成处理器，用于实现用于可重新配置的基于处理器的多模3G无线应用的完整固定速率DRX信号处理路径（FDRX）。 该架构基于16位RISC架构，附加功能块（ADU）与基于处理器的数据路径紧密耦合。 每个ADU加速FDRX信号路径中的计算密集型任务，如多抽头FIR，IIR，复杂域和矢量数据处理。 ADU通过基于加载/存储架构的定制指令进行控制。 整个FDRX数据路径可以通过使用这些定制指令的软件轻松实现。

公开(公告)号：US6005793A

公开(公告)日：1999-12-21

申请号：US52518

申请日：1998-03-31

申请人： Thang Minh Tran

发明人： Thang Minh Tran

IPC分类号： G11C7/18 ,  G11C8/12 ,  G11C11/56 ,  G11C11/00 ,  G11C16/04

CPC分类号： G11C7/18 ,  G11C11/5621 ,  G11C8/12 ,  G11C11/412

摘要： A cache memory consists of plurality of memory bits within a random-access memory (RAM) cell. An extra address decode circuit is needed to select a single memory bit within the multi-bit RAM cell before normal access of RAM array circuit. Combining of multiple bits into a RAM cell reduces the number of interconnections in comparison to single bit RAM cell. This technique eliminates the need to break up the cache array into multiple sets for reducing power dissipation. The area advantages are also from optimal layout of multi-bit RAM cell, address decoder, and sense amplifier unit. Furthermore, the interconnections can be widened to reduce the RC delay as it is a dominating factor in future technology advancement. The multiplexing of the bits are done before the row decoding thus reducing one level of multiplexing after reading of data from the sense amplifier units.

摘要翻译： 高速缓冲存储器由随机存取存储器（RAM）单元内的多个存储器位组成。 在RAM阵列电路正常访问之前，需要一个额外的地址解码电路来选择多位RAM单元内的单个存储器位。 与单位RAM单元相比，将多个比特组合到RAM单元中减少了互连的数量。 这种技术无需将缓存阵列分解成多个集合来减少功耗。 区域优势还来自于多位RAM单元，地址解码器和读出放大器单元的最佳布局。 此外，互连可以扩大，以减少RC延迟，因为它是未来技术进步的主要因素。 这些位的复用在行解码之前完成，从而在从读出放大器单元读取数据之后降低一个复用电平。

公开(公告)号：US6065126A

公开(公告)日：2000-05-16

申请号：US17278

申请日：1998-02-02

申请人： Thang Minh Tran ,  Rupaka Mahalingaiah

发明人： Thang Minh Tran ,  Rupaka Mahalingaiah

IPC分类号： G06F1/10 ,  G06F9/38 ,  G06F1/12

CPC分类号： G06F9/3804 ,  G06F1/10

摘要： A self-timed and self-enabled distributed clock is provided for a functional unit that has variable executing time. The self-timed clock provides plurality of clock pulses within a clock cycle for latching of result and starting execution of the next operation. The functional unit can execute more than one operation per clock cycle thus increasing the utilization of the execute unit and the performance of the processor. The state machine is designed to keep track of the current clock pulse and the execution time of the current operation. The functional unit includes the output queue buffer to keep plurality of results from execute unit. The functional unit executes data close to its optimal timing while the data between functional units are synchronized on the clock boundary as in synchronous design. It is more efficient than synchronous design yet the outputs are deterministic as the clocking is preserved in the design.

摘要翻译： 为具有可变执行时间的功能单元提供自定时和自启动分布式时钟。 自定时钟在时钟周期内提供多个时钟脉冲，用于锁存结果并开始执行下一个操作。 功能单元可以在每个时钟周期执行多个操作，从而增加了执行单元的使用和处理器的性能。 状态机设计用于跟踪当前时钟脉冲和当前操作的执行时间。 功能单元包括输出队列缓冲器，以保持来自执行单元的多个结果。 在同步设计中，功能单元在时钟边界上同步功能单元之间的数据，执行接近其最佳定时的数据。 它比同步设计更有效率，但输出是确定性的，因为设计中保留了时钟。