公开(公告)号：US08010922B2

公开(公告)日：2011-08-30

申请号：US12032762

申请日：2008-02-18

申请人： Frank Malgioglio ,  Adam R. Jatkowski ,  Brian A. Lasseter ,  Joseph J. Palumbo

发明人： Frank Malgioglio ,  Adam R. Jatkowski ,  Brian A. Lasseter ,  Joseph J. Palumbo

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： Buffers are placed on selected nets coupled to input and output pins of entities in an IC device. This includes loading selected input and output pins of entities prior to respectively buffering nets of the entities and buffering in successive iterations, which includes setting artificial loads on selected input pins. The buffering in a current iteration is limited to i) buffering nets on the current iteration entity for receivers on the current iteration entity and ii) buffering nets on the current iteration entity directly coupled to respective nets of an immediately adjacent entity that has been buffered already in a preceding one of iterations, but only if the already buffered net is coupled to a receiver on its own net or a receiver on some other already buffered net via nets that have all been buffered via one or more of the preceding iterations.

摘要翻译： 缓冲器放置在耦合到IC器件中的实体的输入和输出引脚的选定网络上。 这包括在分别缓冲实体的网络和连续迭代中的缓冲之前加载实体的选定输入和输出引脚，其中包括在选定的输入引脚上设置人工负载。 当前迭代中的缓冲被限制为i）在当前迭代实体上的接收器的当前迭代实体上缓冲网络，以及ii）直接耦合到已经被缓冲的紧邻相邻实体的相应网络的当前迭代实体上的缓冲网 在前面的一个迭代中，但是仅当已经缓冲的网络耦合到其自身网络上的接收器或已经经由一个或多个前述迭代缓冲的网络的一些其它已经缓冲的网络上的接收器时。

公开(公告)号：US06629298B1

公开(公告)日：2003-09-30

申请号：US09437844

申请日：1999-11-10

申请人： Peter J. Camporese ,  Adam R. Jatkowski ,  Leon J. Sigal ,  Patrick M. Williams

发明人： Peter J. Camporese ,  Adam R. Jatkowski ,  Leon J. Sigal ,  Patrick M. Williams

IPC分类号： G06F945

CPC分类号： G06F17/5022

摘要： A method (and a system for using the method) for automating a slew rate analysis between two or more circuits on a semiconductor chip. The method includes the steps of: receiving as input one or more input parameters characterizing the physical medium through which the signal propagation occurs (the net) and the electrical characteristics of signals transmitted between the circuits; and providing as output one or more output parameters characterizing the appropriate solution for physical implementation of the circuit(s) and net(s) which satisfy the performance requirements of the system. The receiving step can comprise any one of: providing a hierarchical signal name cross-reference defining a name for the signal for a given hierarchy level of the circuits; providing a set of one or more boolean equations used to generate the one or more output parameters from the one or more input parameters; providing a physical design information for the circuits; and providing a timing information for the signals. The boolean equations can include as input variables: the physical design information for the circuits; and the timing information for the signals. The transmitting step includes the steps of: determining if the signals require one or more buffers; determining if signal pin locations of the circuits through hierarchical levels thereof are not optimal; determining if strengths of transistors driving the signals must be increased; determining if the widths of wires used to transmit the signals must be increased; and determining if wires used to transmit the signals must be on less resistive wiring layers.

摘要翻译： 一种用于使半导体芯片上的两个或多个电路之间的压摆率分析自动化的方法（以及使用该方法的系统）。 该方法包括以下步骤：接收表征信号传播的物理介质（网络）和电路之间传输的信号的电特性作为输入的一个或多个输入参数; 以及作为输出提供一个或多个输出参数，其表征满足系统的性能要求的电路和网络的物理实现的适当解决方案。 接收步骤可以包括以下任何一个：提供定义电路的给定层次级别的信号的名称的分层信号名称交叉引用; 提供用于从所述一个或多个输入参数生成所述一个或多个输出参数的一组或多个布尔方程组; 为电路提供物理设计信息; 并提供信号的定时信息。 布尔方程可以包括输入变量：电路的物理设计信息; 和信号的定时信息。 发送步骤包括以下步骤：确定信号是否需要一个或多个缓冲器; 确定电路的信号引脚位置是否通过其层级不是最佳的; 确定驱动信号的晶体管的强度是否必须增加; 确定用于传输信号的电线宽度是否必须增加; 并且确定用于传输信号的导线是否必须在较小的电阻布线层上。

公开(公告)号：US20090210842A1

公开(公告)日：2009-08-20

申请号：US12032762

申请日：2008-02-18

申请人： Frank Malgioglio ,  Adam R. Jatkowski ,  Brian A. Lasseter ,  Joseph J. Palumbo

发明人： Frank Malgioglio ,  Adam R. Jatkowski ,  Brian A. Lasseter ,  Joseph J. Palumbo

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： Buffers are placed on selected nets coupled to input and output pins of entities in an IC device. This includes loading selected input and output pins of entities prior to respectively buffering nets of the entities and buffering in successive iterations, which includes setting artificial loads on selected input pins. The buffering in a current iteration is limited to i) buffering nets on the current iteration entity for receivers on the current iteration entity and ii) buffering nets on the current iteration entity directly coupled to respective nets of an immediately adjacent entity that has been buffered already in a preceding one of iterations, but only if the already buffered net is coupled to a receiver on its own net or a receiver on some other already buffered net via nets that have all been buffered via one or more of the preceding iterations.

摘要翻译： 缓冲器放置在耦合到IC器件中的实体的输入和输出引脚的选定网络上。 这包括在分别缓冲实体的网络和连续迭代中的缓冲之前加载实体的选定输入和输出引脚，其中包括在选定的输入引脚上设置人工负载。 当前迭代中的缓冲被限制为i）在当前迭代实体上的接收器的当前迭代实体上缓冲网络，以及ii）直接耦合到已经被缓冲的紧邻相邻实体的相应网络的当前迭代实体上的缓冲网 在前面的一个迭代中，但是仅当已经缓冲的网络耦合到其自身网络上的接收器或已经经由一个或多个前述迭代缓冲的网络的一些其它已经缓冲的网络上的接收器时。

公开(公告)号：US07568176B2

公开(公告)日：2009-07-28

申请号：US11757457

申请日：2007-06-04

申请人： Adam R. Jatkowski ,  Robert M. Averill, III ,  Joseph J. Palumbo

发明人： Adam R. Jatkowski ,  Robert M. Averill, III ,  Joseph J. Palumbo

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： A method, system, and computer program product for hierarchical integrated circuit repartitioning are provided. The method includes receiving parent level placement data for one or more interconnecting elements and designating at least one child to receive a pushdown of the one or more interconnecting elements from the parent level. For each child designated to receive the pushdown of the one or more interconnecting elements, the method further includes determining a physical coverage area of the child, identifying which of the one or more interconnecting elements within the physical coverage area of the child to pushdown into the child, generating an interconnecting element pushdown list for the child, including wiring layer information, and outputting the interconnecting element pushdown list.

摘要翻译： 提供了一种用于分级集成电路重新分配的方法，系统和计算机程序产品。 该方法包括接收一个或多个互连元件的父级放置数据，并且指定至少一个子级以从母级接收一个或多个互连元件的下推。 对于被指定为接收一个或多个互连元件的下推的每个孩子，该方法还包括确定儿童的物理覆盖区域，识别儿童的物理覆盖区域内的一个或多个互连元件中的哪一个向下推入 孩子，为孩子生成互连元件下拉列表，包括布线层信息，以及输出互连元件下推列表。

公开(公告)号：US20080301607A1

公开(公告)日：2008-12-04

申请号：US11757457

申请日：2007-06-04

申请人： Adam R. Jatkowski ,  Robert M. Averill, III ,  Joseph J. Palumbo

发明人： Adam R. Jatkowski ,  Robert M. Averill, III ,  Joseph J. Palumbo

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： A method, system, and computer program product for hierarchical integrated circuit repartitioning are provided. The method includes receiving parent level placement data for one or more interconnecting elements and designating at least one child to receive a pushdown of the one or more interconnecting elements from the parent level. For each child designated to receive the pushdown of the one or more interconnecting elements, the method further includes determining a physical coverage area of the child, identifying which of the one or more interconnecting elements within the physical coverage area of the child to pushdown into the child, generating an interconnecting element pushdown list for the child, including wiring layer information, and outputting the interconnecting element pushdown list.

摘要翻译： 提供了一种用于分级集成电路重新分配的方法，系统和计算机程序产品。 该方法包括接收一个或多个互连元件的父级放置数据，并且指定至少一个子级以从母级接收一个或多个互连元件的下推。 对于被指定为接收一个或多个互连元件的下推的每个孩子，该方法还包括确定儿童的物理覆盖区域，识别儿童的物理覆盖区域内的一个或多个互连元件中的哪一个向下推入 孩子，为孩子生成互连元件下拉列表，包括布线层信息，以及输出互连元件下推列表。