Low latency system bus interface for multi-master processing environments
    1.
    发明授权
    Low latency system bus interface for multi-master processing environments 有权
    用于多主处理环境的低延迟系统总线接口

    公开(公告)号:US06732208B1

    公开(公告)日:2004-05-04

    申请号:US09318551

    申请日:1999-05-27

    IPC分类号: G06F1300

    CPC分类号: G06F12/0831 G06F12/0835

    摘要: A bus interface to a split transaction computing bus having separate address and data portions is provided. The bus interface contains separate address and data interfaces for initiating and tracking out-of-order transactions on either or both of the address or data portions of the computing bus. The bus interface includes split transaction tracking and control to establish transaction ID's for each transaction initiated by the bus interface, and to determine whether data appearing on the data portion of the computing bus is associated with one of its pending transactions. The bus interface also contains flow control logic to determine whether devices that are to be read from, or written to, by the bus interface, have resources (buffers) available to respond to the transactions. If the resources are available, the flow control logic allows the transactions to proceed, and adjusts its counters to reflect the use of the resources. If the resources are not available, the flow control logic causes the transactions to wait until the resources become available. Snoop control logic is also provided to insure coherency between multiple instances of data within devices attached to the split transaction bus. Data release logic drives a data release signal on the last cycle of a data transaction to reduce latency between sequential data transactions by one or more masters on the computing bus.

    摘要翻译: 提供了具有分离的地址和数据部分的分离事务计算总线的总线接口。 总线接口包含单独的地址和数据接口,用于在计算总线的地址或数据部分的一个或两个上启动和跟踪无序事务。 总线接口包括拆分事务跟踪和控制,以为由总线接口发起的每个事务建立事务ID,并确定出现在计算总线的数据部分上的数据是否与其未完成的事务之一相关联。 总线接口还包含流控制逻辑,以确定要由总线接口读取或写入的器件是否具有可用于响应事务的资源(缓冲器)。 如果资源可用,流控制逻辑允许事务进行,并调整其计数器以反映资源的使用。 如果资源不可用,则流控制逻辑导致事务等待直到资源变得可用。 还提供了侦听控制逻辑以确保连接到拆分事务总线的设备内的数据的多个实例之间的一致性。 数据释放逻辑在数据事务的最后一个周期驱动数据释放信号,以减少计算总线上的一个或多个主器件在顺序数据事务之间的延迟。