公开(公告)号：US10339068B2

公开(公告)日：2019-07-02

申请号：US15495707

申请日：2017-04-24

Applicant: Advanced Mirco Devices, Inc. ,  ATI Technologies ULC

Inventor： Wade K. Smith ,  Anthony Asaro

IPC: G06F12/1045 ,  G06F12/1027 ,  G06F12/1009

Abstract: Systems, apparatuses, and methods for implementing a virtualized translation lookaside buffer (TLB) are disclosed herein. In one embodiment, a system includes at least an execution unit and a first TLB. The system supports the execution of a plurality of virtual machines in a virtualization environment. The system detects a translation request generated by a first virtual machine with a first virtual memory identifier (VMID). The translation request is conveyed from the execution unit to the first TLB. The first TLB performs a lookup of its cache using at least a portion of a first virtual address and the first VMID. If the lookup misses in the cache, the first TLB allocates an entry which is addressable by the first virtual address and the first VMID, and the first TLB sends the translation request with the first VMID to a second TLB.

公开(公告)号：US20030074493A1

公开(公告)日：2003-04-17

申请号：US10093346

申请日：2002-03-07

Applicant: Advanced Mirco Devices, Inc.

Inventor： Tahsin Askar ,  James R. Magro

IPC: G06F003/00

CPC classification number: G06F13/128

Abstract: A peripheral interface circuit for handling graphics responses in an I/O node of a computer system. A peripheral interface circuit includes a buffer circuit coupled to receive packet commands. The buffer circuit includes a plurality of buffers each corresponding to a respective virtual channel of a plurality of virtual channels for storing selected packet commands that belong to the respective virtual channel. The peripheral interface circuit may determine whether a given one of the received packet commands is a graphics response belonging to a particular respective virtual channel. In response to determining that the given packet command is a graphics response belonging to the particular respective virtual channel, the buffer circuit may cause the given packet command to bypass the plurality of buffers.

Abstract translation: 一种用于处理计算机系统的I / O节点中的图形响应的外围接口电路。 外围接口电路包括耦合以接收分组命令的缓冲电路。 缓冲电路包括多个缓冲器，每个缓冲器对应于多个虚拟通道的相应虚拟通道，用于存储属于相应虚拟通道的所选择的分组命令。 外围接口电路可以确定所接收的分组命令中的给定的一个是属于特定的相应虚拟信道的图形响应。 响应于确定给定分组命令是属于特定相应虚拟信道的图形响应，缓冲器电路可以使给定分组命令绕过多个缓冲器。