公开(公告)号：US4723205A

公开(公告)日：1988-02-02

申请号：US814076

申请日：1985-12-23

Applicant: Joji Fukuda ,  Akira Takezawa ,  Yutaka Ohkubo ,  Kenichi Kobayashi ,  Toshinori Nakamura

Inventor： Joji Fukuda ,  Akira Takezawa ,  Yutaka Ohkubo ,  Kenichi Kobayashi ,  Toshinori Nakamura

IPC: G06F15/16 ,  G06F13/40 ,  G06F15/17 ,  G06F15/177 ,  G06F13/00 ,  G06F13/38

CPC classification number: G06F15/17 ,  G06F13/4018

Abstract: A microcomputer system has two central processing units, an original and one added to expand the system, each having an associated memory and being interconnected through an appropriate signal bus arrangement, however, only the first or original central processing unit employs an input/output device for inputting/outputting data; a bus controller and bus arbiter including a status signal generator are connected to the signal bus to provide addresses to permit the second or added central processing unit to be mapped onto the input/output address of the first central processing unit. The first central processing unit and its associated memory circuits and buses and the like then appear as peripherals with direct memory access from the viewpoint of the second or added central processing unit. A priority decoder is provided to insure that the first central processing unit has bus priority over the second central processing unit.

Abstract translation: 微型计算机系统具有两个中央处理单元，一个原始的和一个附加的扩展系统，每个都具有相关的存储器并通过适当的信号总线布置互连，然而，只有第一或者原始的中央处理单元采用输入/输出设备 用于输入/输出数据; 包括状态信号发生器的总线控制器和总线仲裁器连接到信号总线以提供地址，以允许第二或附加的中央处理单元映射到第一中央处理单元的输入/输出地址。 因此，从第二或附加的中央处理单元的观点来看，第一中央处理单元及其关联的存储器电路和总线等似乎是具有直接存储器访问的外围设备。 提供优先级解码器以确保第一中央处理单元具有超过第二中央处理单元的总线优先级。