公开(公告)号：US20090083685A1

公开(公告)日：2009-03-26

申请号：US12324742

申请日：2008-11-26

申请人： Alexander GIDON ,  David Knapp

发明人： Alexander GIDON ,  David Knapp

IPC分类号： G06F17/50 ,  G06F7/38

CPC分类号： G06F17/505

摘要： A method for generating timing constraint systems, where the constrained object is a digital circuit, is provided, where the constraints are generated for the use of a digital logic optimization (synthesis) tool. The synthesis tool is used to optimize the circuit, under the applied constraints, so that the circuit exhibits certain desirable timing properties, while at the same time minimizing hardware cost and various other properties. The particular class of timing constraints generated by the disclosed invention is useful when the circuit is to be retimed after optimization. Typically, the joint use of the described invention and retiming results in improvements in the overall cost/performance tradeoff curve of the design. The invention comprises a method that comprises the following steps: (1) the flip-flops of the design are replaced with buffers having a negative delay whose magnitude is approximately the desired clock cycle time of the design; and (2) cycles in the design are broken using flip-flops having an infinite or quasi-infinite clock frequency. Following optimization by the synthesis tool, the temporary changes can be reverted, and retiming performed on the circuit.

摘要翻译： 提供了一种用于产生定时约束系统的方法，其中约束对象是数字电路，其中为使用数字逻辑优化（综合）工具生成约束。 该合成工具用于在施加的约束条件下优化电路，使得电路具有某些期望的时序特性，同时最小化硬件成本和各种其它特性。 当所述电路在优化之后被重新定时时，由所公开的发明产生的特定类别的时序约束是有用的。 通常，联合使用所描述的发明和重新定时导致设计的整体成本/性能折衷曲线的改进。 本发明包括一种方法，其包括以下步骤：（1）设计的触发器被具有负延迟的缓冲器替换，其幅度近似为设计的期望时钟周期时间; 并且（2）设计中的周期使用具有无限或准无限时钟频率的触发器来断开。 通过综合工具进行优化后，可以恢复临时更改，并对电路进行重新定时。

公开(公告)号：US08060844B2

公开(公告)日：2011-11-15

申请号：US12324742

申请日：2008-11-26

申请人： Alexander Gidon ,  David Knapp

发明人： Alexander Gidon ,  David Knapp

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： A method for generating timing constraint systems, where the constrained object is a digital circuit, is provided, where the constraints are generated for the use of a digital logic optimization (synthesis) tool. The synthesis tool is used to optimize the circuit, under the applied constraints, so that the circuit exhibits certain desirable timing properties, while at the same time minimizing hardware cost and various other properties. The particular class of timing constraints generated by the disclosed invention is useful when the circuit is to be retimed after optimization. Typically, the joint use of the described invention and retiming results in improvements in the overall cost/performance tradeoff curve of the design. The invention comprises a method that comprises the following steps: (1) the flip-flops of the design are replaced with buffers having a negative delay whose magnitude is approximately the desired clock cycle time of the design; and (2) cycles in the design are broken using flip-flops having an infinite or quasi-infinite clock frequency. Following optimization by the synthesis tool, the temporary changes can be reverted, and retiming performed on the circuit.

摘要翻译： 提供了一种用于产生定时约束系统的方法，其中约束对象是数字电路，其中为使用数字逻辑优化（综合）工具生成约束。 该合成工具用于在施加的约束条件下优化电路，使得电路具有某些期望的时序特性，同时最小化硬件成本和各种其它特性。 当所述电路在优化之后被重新定时时，由所公开的发明产生的特定类别的时序约束是有用的。 通常，联合使用所描述的发明和重新定时导致设计的整体成本/性能折衷曲线的改进。 本发明包括一种方法，其包括以下步骤：（1）设计的触发器被具有负延迟的缓冲器替换，其幅度近似为设计的期望时钟周期时间; 并且（2）设计中的周期使用具有无限或准无限时钟频率的触发器来断开。 通过综合工具进行优化后，可以恢复临时更改，并对电路进行重新定时。

公开(公告)号：US07584441B2

公开(公告)日：2009-09-01

申请号：US10665880

申请日：2003-09-19

申请人： Alexander Gidon ,  David Knapp

发明人： Alexander Gidon ,  David Knapp

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： A method for generating timing constraint systems, where the constrained object is a digital circuit., is provided, where the constraints are generated for the use of a digital logic optimization (synthesis) tool. The synthesis tool is used to optimize the circuit, under the applied constraints, so that the circuit exhibits certain desirable timing properties, while at the same time minimizing hardware cost and various other properties. The particular class of timing constraints generated by the disclosed invention is useful when the circuit is to be retimed after optimization. Typically, the joint use of the described invention and retiming results in improvements in the overall cost/performance tradeoff curve of the design. The invention comprises a method that comprises the following steps: (1) the flip-flops of the design are replaced with buffers having a negative delay whose magnitude is approximately the desired clock cycle time of the design; and (2) cycles in the design are broken using flip-flops having an infinite or quasi-infinite clock frequency. Following optimization by the synthesis tool, the temporary changes can be reverted, and retiming performed on the circuit.

摘要翻译： 提供了一种用于产生定时约束系统的方法，其中约束对象是数字电路，其中为使用数字逻辑优化（综合）工具生成约束。 该合成工具用于在施加的约束条件下优化电路，使得电路具有某些期望的时序特性，同时最小化硬件成本和各种其它特性。 当所述电路在优化之后被重新定时时，由所公开的发明产生的特定类别的时序约束是有用的。 通常，联合使用所描述的发明和重新定时导致设计的整体成本/性能折衷曲线的改进。 本发明包括一种方法，其包括以下步骤：（1）设计的触发器被具有负延迟的缓冲器替换，其幅度近似为设计的期望时钟周期时间; 并且（2）设计中的周期使用具有无限或准无限时钟频率的触发器来断开。 通过综合工具进行优化后，可以恢复临时更改，并对电路进行重新定时。

公开(公告)号：US20050062496A1

公开(公告)日：2005-03-24

申请号：US10665880

申请日：2003-09-19

申请人： Alexander Gidon ,  David Knapp

发明人： Alexander Gidon ,  David Knapp

IPC分类号： G06F20060101 ,  G06F7/38 ,  G06F17/50

CPC分类号： G06F17/505

摘要： A method for generating timing constraint systems, where the constrained object is a digital circuit., is provided, where the constraints are generated for the use of a digital logic optimization (synthesis) tool. The synthesis tool is used to optimize the circuit, under the applied constraints, so that the circuit exhibits certain desirable timing properties, while at the same time minimizing hardware cost and various other properties. The particular class of timing constraints generated by the disclosed invention is useful when the circuit is to be retimed after optimization. Typically, the joint use of the described invention and retiming results in improvements in the overall cost/performance tradeoff curve of the design. The invention comprises a method that comprises the following steps: (1) the flip-flops of the design are replaced with buffers having a negative delay whose magnitude is approximately the desired clock cycle time of the design; and (2) cycles in the design are broken using flip-flops having an infinite or quasi-infinite clock frequency. Following optimization by the synthesis tool, the temporary changes can be reverted, and retiming performed on the circuit.

摘要翻译： 提供了一种用于产生定时约束系统的方法，其中约束对象是数字电路，其中为使用数字逻辑优化（综合）工具生成约束。 该合成工具用于在施加的约束条件下优化电路，使得电路具有某些期望的时序特性，同时最小化硬件成本和各种其它特性。 当所述电路在优化之后被重新定时时，由所公开的发明产生的特定类别的时序约束是有用的。 通常，联合使用所描述的发明和重新定时导致设计的整体成本/性能折衷曲线的改进。 本发明包括一种方法，其包括以下步骤：（1）设计的触发器被具有负延迟的缓冲器替换，其幅度近似为设计的期望时钟周期时间; 并且（2）设计中的周期使用具有无限或准无限时钟频率的触发器来断开。 通过综合工具进行优化后，可以恢复临时更改，并对电路进行重新定时。